公开(公告)号：US10014216B2

公开(公告)日：2018-07-03

申请号：US14854221

申请日：2015-09-15

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Sanghyeon Kim ,  Daemyeong Geum ,  Min Su Park ,  Won Jun Choi

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/36 ,  H01L21/78 ,  H01L21/683 ,  H01L21/18 ,  H01L31/0304 ,  H01L29/267 ,  H01L29/66 ,  H01L29/861 ,  H01L29/20

CPC classification number: H01L21/78 ,  H01L21/185 ,  H01L21/6835 ,  H01L29/267 ,  H01L29/66219 ,  H01L29/861 ,  H01L31/0304 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/544 ,  Y02P70/521

Abstract: Disclosed is a method for manufacturing a semiconductor device, which includes providing a template having a first substrate and a patterned first III-V group compound layer located on the first substrate, forming a sacrificial layer on the patterned first III-V group compound layer by epitaxial growth, forming a second III-V group compound layer on the sacrificial layer by epitaxial growth, bonding a second substrate made of silicon onto the second III-V group compound layer, and separating the second III-V group compound layer and the second substrate from the template by removing the sacrificial layer.