公开(公告)号：US20050248385A1

公开(公告)日：2005-11-10

申请号：US11016712

申请日：2004-12-21

Applicant: Kang-Seol Lee ,  Jae-Jin Lee

Inventor： Kang-Seol Lee ,  Jae-Jin Lee

IPC: G11C5/14 ,  H03K3/38

CPC classification number: G11C5/145

Abstract: The present invention provides voltage supplier for supplying an internal voltage with optimized drivability required for internal operation. The voltage supplier of a semiconductor memory device includes: an internal voltage detection means for detecting a voltage level of an internal voltage; a clock oscillation means for outputting a charge pumping clock signal; an internal voltage control means for controlling the clock oscillation means to be performed selectively in accordance with a data access mode or a non-data access mode; and a charge pumping means for outputting the internal voltage required for internal operation by pumping charges in response to the charge pumping clock signal.

Abstract translation: 本发明提供了一种内部电压提供内部操作所需的最佳驾驶性能的电压供应器。 半导体存储器件的电压供应器包括：内部电压检测装置，用于检测内部电压的电压电平; 时钟振荡装置，用于输出电荷泵送时钟信号; 内部电压控制装置，用于根据数据存取模式或非数据存取模式选择性地控制时钟振荡装置; 以及电荷泵送装置，用于响应于电荷泵送时钟信号，通过泵送电荷来输出内部操作所需的内部电压。

公开(公告)号：US20070070720A1

公开(公告)日：2007-03-29

申请号：US11478192

申请日：2006-06-30

Applicant: Kang-Seol Lee ,  Jae-Jin Lee

Inventor： Kang-Seol Lee ,  Jae-Jin Lee

IPC: G11C5/14

CPC classification number: G11C5/14

Abstract: A voltage generator for use in a semiconductor memory device includes an output voltage controller for generating a bias voltage using a reference voltage of which a voltage level is half of a core voltage level. Pull-up/pull-down driving signals are output by generating a voltage which is higher or lower than the reference voltage by a threshold voltage. An output driver generates a bit line precharge voltage in response to the pull-up driving signal or the pull-down driving signal. Drive controllers interrupt off-leakage current of the output driver. One drive controller is disposed between the output driver and a core voltage terminal and another drive controller is between the output driver and a ground voltage terminal.

Abstract translation: 用于半导体存储器件的电压发生器包括：输出电压控制器，用于使用电压电平为核心电压电平的一半的参考电压产生偏置电压。 通过产生高于或低于参考电压阈值电压的电压来输出上拉/下拉驱动信号。 输出驱动器响应于上拉驱动信号或下拉驱动信号产生位线预充电电压。 驱动控制器会中断输出驱动器的漏电流。 一个驱动控制器设置在输出驱动器和核心电压端子之间，另一个驱动控制器位于输出驱动器和地电压端子之间。

公开(公告)号：US07579821B2

公开(公告)日：2009-08-25

申请号：US11529255

申请日：2006-09-29

Applicant: Kang-Seol Lee ,  Jae-Jin Lee

Inventor： Kang-Seol Lee ,  Jae-Jin Lee

IPC: G06F3/16

CPC classification number: G05F3/242 ,  G11C5/147 ,  G11C7/12

Abstract: A voltage generator includes a bias signal generator generating first to fourth bias signals using a reference voltage, the first to fourth bias signals having different voltage levels. A driving signal generator receives the first and third bias signals to generate a pull-up signal in response to a voltage level of an output terminal and receiving the second and fourth bias signals to generate a pull-down signal in response to a voltage level of the output terminal. A voltage driver pulls up and pulls down a voltage level of the output terminal in response to the respective pull-up and pull-down signals. An auxiliary driving controller disables the pull-up signal when the voltage level of the output terminal is greater than that of the reference voltage and the pull-down signal when the voltage level of the output terminal is less than that of the reference voltage.

Abstract translation: 电压发生器包括利用参考电压产生第一至第四偏置信号的偏置信号发生器，第一至第四偏置信号具有不同的电压电平。 驱动信号发生器接收第一和第三偏置信号以响应于输出端的电压电平产生上拉信号，并且接收第二和第四偏置信号以响应于电压电平产生下拉信号 输出端子。 电压驱动器响应于相应的上拉和下拉信号而拉出并拉低输出端子的电压电平。 当输出端子的电压电平小于参考电压的电平时，辅助驱动控制器在输出端子的电压电平大于参考电压的电压电平和下拉信号时，禁用上拉信号。

公开(公告)号：US20080129373A1

公开(公告)日：2008-06-05

申请号：US12027089

申请日：2008-02-06

Applicant: Kang-Seol LEE ,  Jae-Jin Lee

Inventor： Kang-Seol LEE ,  Jae-Jin Lee

IPC: G05F3/02

CPC classification number: G11C5/145

Abstract: The present invention provides voltage supplier for supplying an internal voltage with optimized drivability required for internal operation. The voltage supplier of a semiconductor memory device includes: an internal voltage detection means for detecting a voltage level of an internal voltage; a clock oscillation means for outputting a charge pumping clock signal; an internal voltage control means for controlling the clock oscillation means to be performed selectively in accordance with a data access mode or a non-data access mode; and a charge pumping means for outputting the internal voltage required for internal operation by pumping charges in response to the charge pumping clock signal.

Abstract translation: 本发明提供了一种内部电压提供内部操作所需的最佳驾驶性能的电压供应器。 半导体存储器件的电压供应器包括：内部电压检测装置，用于检测内部电压的电压电平; 时钟振荡装置，用于输出电荷泵送时钟信号; 内部电压控制装置，用于根据数据访问模式或非数据访问模式选择性地控制时钟振荡装置; 以及电荷泵送装置，用于响应于电荷泵送时钟信号，通过泵送电荷来输出内部操作所需的内部电压。

公开(公告)号：US20070069710A1

公开(公告)日：2007-03-29

申请号：US11529255

申请日：2006-09-29

Applicant: Kang-Seol Lee ,  Jae-Jin Lee

Inventor： Kang-Seol Lee ,  Jae-Jin Lee

IPC: G05F3/16

CPC classification number: G05F3/242 ,  G11C5/147 ,  G11C7/12

Abstract: A voltage generator includes a bias signal generator generating first to fourth bias signals using a reference voltage, the first to fourth bias signals having different voltage levels. A driving signal generator receives the first and third bias signals to generate a pull-up signal in response to a voltage level of an output terminal and receiving the second and fourth bias signals to generate a pull-down signal in response to a voltage level of the output terminal. A voltage driver pulls up and pulls down a voltage level of the output terminal in response to the respective pull-up and pull-down signals. An auxiliary driving controller disables the pull-up signal when the voltage level of the output terminal is greater than that of the reference voltage and the pull-down signal when the voltage level of the output terminal is less than that of the reference voltage.

Abstract translation: 电压发生器包括利用参考电压产生第一至第四偏置信号的偏置信号发生器，第一至第四偏置信号具有不同的电压电平。 驱动信号发生器接收第一和第三偏置信号以响应于输出端的电压电平产生上拉信号，并且接收第二和第四偏置信号以响应于电压电平产生下拉信号 输出端子。 电压驱动器响应于相应的上拉和下拉信号而拉出并拉低输出端子的电压电平。 当输出端子的电压电平小于参考电压的电平时，辅助驱动控制器在输出端子的电压电平大于参考电压的电压电平和下拉信号时，禁止上拉信号。

公开(公告)号：US07113440B2

公开(公告)日：2006-09-26

申请号：US10877555

申请日：2004-06-24

Applicant: Kang-Seol Lee ,  Jae-Jin Lee

Inventor： Kang-Seol Lee ,  Jae-Jin Lee

IPC: G11C7/00

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4068

Abstract: A semiconductor memory device includes: a self refresh request signal generation unit which receives a self refresh signal for generating a base periodic signal, a plurality of divided signals and a self refresh request signal; an internal voltage generation control signal generation unit for generating an internal voltage generation control signal in response to the plurality of divided signals; and an internal voltage generation unit for generating an internal voltage in response to the internal voltage generation control signal.

Abstract translation: 半导体存储器件包括：自刷新请求信号生成单元，其接收用于生成基本周期信号的自刷新信号，多个分割信号和自刷新请求信号; 内部电压产生控制信号生成单元，用于响应于所述多个分割信号产生内部电压产生控制信号; 以及用于响应于内部电压产生控制信号产生内部电压的内部电压产生单元。

公开(公告)号：US08564138B2

公开(公告)日：2013-10-22

申请号：US13196320

申请日：2011-08-02

Applicant: Kang-Seol Lee ,  Jae-Jin Lee ,  Jae-Hyuk Im

Inventor： Kang-Seol Lee ,  Jae-Jin Lee ,  Jae-Hyuk Im

IPC: H01L23/48

CPC classification number: H01L23/50 ,  H01L23/481 ,  H01L23/5286 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction.

Abstract translation: 半导体集成电路包括半导体芯片，垂直穿过半导体芯片形成并被配置为用作第一电源的接口的多个第一通孔通孔和设置在半导体芯片上的第一公共导电层， 多个第一通过芯片通孔在水平方向上彼此相对。

公开(公告)号：US07514986B2

公开(公告)日：2009-04-07

申请号：US12027089

申请日：2008-02-06

Applicant: Kang-Seol Lee ,  Jae-Jin Lee

Inventor： Kang-Seol Lee ,  Jae-Jin Lee

IPC: G05F1/10

CPC classification number: G11C5/145

Abstract: The present invention provides voltage supplier for supplying an internal voltage with optimized drivability required for internal operation. The voltage supplier of a semiconductor memory device includes: an internal voltage detection means for detecting a voltage level of an internal voltage; a clock oscillation means for outputting a charge pumping clock signal; an internal voltage control means for controlling the clock oscillation means to be performed selectively in accordance with a data access mode or a non-data access mode; and a charge pumping means for outputting the internal voltage required for internal operation by pumping charges in response to the charge pumping clock signal.

Abstract translation: 本发明提供了一种内部电压提供内部操作所需的最佳驾驶性能的电压供应器。 半导体存储器件的电压供应器包括：内部电压检测装置，用于检测内部电压的电压电平; 时钟振荡装置，用于输出电荷泵送时钟信号; 内部电压控制装置，用于根据数据存取模式或非数据存取模式选择性地控制时钟振荡装置; 以及电荷泵送装置，用于响应于电荷泵送时钟信号，通过泵送电荷来输出内部操作所需的内部电压。

公开(公告)号：US07348828B2

公开(公告)日：2008-03-25

申请号：US11016712

申请日：2004-12-21

Applicant: Kang-Seol Lee ,  Jae-Jin Lee

Inventor： Kang-Seol Lee ,  Jae-Jin Lee

IPC: G05F1/10

CPC classification number: G11C5/145

Abstract: The present invention provides voltage supplier for supplying an internal voltage with optimized drivability required for internal operation. The voltage supplier of a semiconductor memory device includes: an internal voltage detection means for detecting a voltage level of an internal voltage; a clock oscillation means for outputting a charge pumping clock signal; an internal voltage control means for controlling the clock oscillation means to be performed selectively in accordance with a data access mode or a non-data access mode; and a charge pumping means for outputting the internal voltage required for internal operation by pumping charges in response to the charge pumping clock signal.

Abstract translation: 本发明提供了一种内部电压提供内部操作所需的最佳驾驶性能的电压供应器。 半导体存储器件的电压供应器包括：内部电压检测装置，用于检测内部电压的电压电平; 时钟振荡装置，用于输出电荷泵送时钟信号; 内部电压控制装置，用于根据数据存取模式或非数据存取模式选择性地控制时钟振荡装置; 以及电荷泵送装置，用于响应于电荷泵送时钟信号，通过泵送电荷来输出内部操作所需的内部电压。

公开(公告)号：US20050141310A1

公开(公告)日：2005-06-30

申请号：US10877555

申请日：2004-06-24

Applicant: Kang-Seol Lee ,  Jae-Jin Lee

Inventor： Kang-Seol Lee ,  Jae-Jin Lee

IPC: G11C11/403 ,  G11C7/00 ,  G11C11/402 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4068

Abstract: A semiconductor memory device includes: a self refresh request signal generation unit which receives a self refresh signal for generating a base periodic signal, a plurality of divided signals and a self refresh request signal; an internal voltage generation control signal generation unit for generating an internal voltage generation control signal in response to the plurality of divided signals; and an internal voltage generation unit for generating an internal voltage in response to the internal voltage generation control signal.

Abstract translation: 半导体存储器件包括：自刷新请求信号生成单元，其接收用于生成基本周期信号的自刷新信号，多个分割信号和自刷新请求信号; 内部电压产生控制信号生成单元，用于响应于所述多个分割信号产生内部电压产生控制信号; 以及用于响应于内部电压产生控制信号产生内部电压的内部电压产生单元。