公开(公告)号：US08837191B2

公开(公告)日：2014-09-16

申请号：US13167963

申请日：2011-06-24

Applicant: Heat Bit Park ,  Kang Seol Lee

Inventor： Heat Bit Park ,  Kang Seol Lee

IPC: G11C5/06

CPC classification number: G06F13/385

Abstract: A semiconductor apparatus includes a multi-chip module which multi-chip module comprises a first and a second chips. The semiconductor apparatus comprises a first data line in the first chip to carry first read data; a first controller, in the first chip, configured to generate first output data on a first output data line in the first chip based on the first read data transmitted from the first data line; a first data transmitter configured to electrically connect the first output data line to the second chip.

Abstract translation: 半导体装置包括多芯片模块，该多芯片模块包括第一芯片和第二芯片。 半导体装置包括第一芯片中的第一数据线，以承载第一读取数据; 第一芯片中的第一控制器被配置为基于从第一数据线发送的第一读取数据在第一芯片中的第一输出数据线上生成第一输出数据; 第一数据发射机，被配置为将所述第一输出数据线电连接到所述第二芯片。

公开(公告)号：US08779571B2

公开(公告)日：2014-07-15

申请号：US13101660

申请日：2011-05-05

Applicant: Kang-Seol Lee

Inventor： Kang-Seol Lee

IPC: H01L29/788 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/06 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5286 ,  H01L25/0657 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An integrated circuit includes a first semiconductor chip including a plurality of first through chip vias for a first voltage and a plurality of second through chip vias for a second voltage inserted in vertical direction. A second semiconductor chip is stacked over the first semiconductor chip, and includes the plurality of first through chip vias and the plurality of second through chip vias. The plurality of first connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding first through chip vias. The plurality of second connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding second through chip vias. A first conductive line is configured to couple the plurality of first connection pads to each other, and a second conductive line is configured to couple the plurality of second connection pads to each other. An isolation layer is inserted between the first conductive line and the second conductive line.

Abstract translation: 集成电路包括第一半导体芯片，其包括用于第一电压的多个第一至第二通孔和用于在垂直方向上插入的第二电压的多个第二至第二通孔。 第二半导体芯片堆叠在第一半导体芯片上，并且包括多个第一至第二通孔和多个第二至第二通孔。 多个第一连接焊盘被配置为通过耦合相应的第一通过芯片通孔来将第一半导体芯片耦合到第二半导体芯片。 多个第二连接焊盘被配置为通过耦合相应的第二贯通芯片通孔来将第一半导体芯片耦合到第二半导体芯片。 第一导电线被配置为将多个第一连接焊盘彼此耦合，并且第二导线被配置为将多个第二连接焊盘彼此耦合。 隔离层插入在第一导线和第二导线之间。

公开(公告)号：US08400136B2

公开(公告)日：2013-03-19

申请号：US12198562

申请日：2008-08-26

Applicant: Kang Seol Lee

Inventor： Kang Seol Lee

IPC: G05F3/16

CPC classification number: G05F3/267 ,  G06F17/5068

Abstract: A semiconductor device and a layout method of the same reduce a mismatch in a semiconductor device. The semiconductor device includes a first transistor unit providing a first path of current and a second transistor unit designed in a mirror structure to the first transistor unit and providing a second path of current. The layout of the second transistor unit has a shape identical to the first transistor unit and shifted in a first direction. The layout of the semiconductor device reduces a mismatch of the transistors occurring when masks are combined, and thereby reduces their offset.

Abstract translation: 半导体器件及其布置方法减少半导体器件中的失配。 该半导体器件包括提供电流的第一路径的第一晶体管单元和以第一晶体管单元的镜结构设计并提供第二电流路径的第二晶体管单元。 第二晶体管单元的布局具有与第一晶体管单元相同的形状并沿第一方向移位。 半导体器件的布局减少了当掩模组合时发生的晶体管的失配，从而减小它们的偏移。

公开(公告)号：US20120287699A1

公开(公告)日：2012-11-15

申请号：US13355781

申请日：2012-01-23

Applicant: Tae Sik YUN ,  Kang Seol LEE

Inventor： Tae Sik YUN ,  Kang Seol LEE

IPC: G11C11/24 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C11/4076 ,  G11C11/4091 ,  G11C11/4099

Abstract: A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a selected memory cell. This technique advantageously compensates capacitance of the bit line. The semiconductor memory device comprises a selected memory cell connected to a first bit line and a first word line, a dummy memory cell connected to a second bit line complementary to the first bit line and a second word line, and a sense amplifier connected to the first and second bit lines and configured to read data stored in the selected memory cell by simultaneously enablement of the first and second word lines.

Abstract translation: 半导体存储器件选择多个存储单元中的一个作为虚拟存储单元。 虚拟存储器单元连接到与连接到所选存储单元的位线互补的位线。 该技术有利地补偿位线的电容。 半导体存储器件包括连接到第一位线和第一字线的选定存储器单元，连接到与第一位线互补的第二位线和第二字线的虚拟存储器单元，以及连接到第一位线的读出放大器 第一和第二位线，并且被配置为通过同时启用第一和第二字线来读取存储在所选存储单元中的数据。

公开(公告)号：US20120267790A1

公开(公告)日：2012-10-25

申请号：US13196320

申请日：2011-08-02

Applicant: Kang-Seol LEE ,  Jae-Jin LEE ,  Jae-Hyuk IM

Inventor： Kang-Seol LEE ,  Jae-Jin LEE ,  Jae-Hyuk IM

IPC: H01L23/48

CPC classification number: H01L23/50 ,  H01L23/481 ,  H01L23/5286 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction.

Abstract translation: 半导体集成电路包括半导体芯片，垂直穿过半导体芯片形成并被配置为用作第一电源的接口的多个第一通孔通孔和设置在半导体芯片上的第一公共导电层， 多个第一通过芯片通孔在水平方向上彼此相对。

公开(公告)号：US20120218843A1

公开(公告)日：2012-08-30

申请号：US13406117

申请日：2012-02-27

Applicant: Tae Sik YUN ,  Kang Seol LEE

Inventor： Tae Sik YUN ,  Kang Seol LEE

IPC: G11C11/406 ,  G11C7/22

CPC classification number: G11C11/40618 ,  G11C29/783

Abstract: Provided is a semiconductor device which performs a refresh operation by sequentially counting a refresh address including a main word line address, a mat address, and a sub word line address in order of the main word line address, the mat address, and the sub word line address. The semiconductor device includes a control signal generation unit configured to activate, latch, and output a toggle control signal when a delayed refresh signal is inputted at the initial stage, deactivate and output the toggle control signal after additionally counting a redundancy word line address when counting of the main word line address with respect to the mat address is completed, and then activate, latch, and output the toggle control signal when the delayed refresh signal is inputted.

Abstract translation: 提供一种半导体器件，其通过按照主字线地址，子地址和子字的顺序依次计数包括主字线地址，字地址和子字线地址的刷新地址来执行刷新操作 行地址。 该半导体装置包括：控制信号生成单元，被配置为当在初始阶段输入延迟的刷新信号时激活，锁存和输出触发控制信号，在对计数后的冗余字线地址进行额外计数之后停用并输出触发控制信号 完成相对于地址地址的主字线地址，然后当延迟刷新信号被输入时，激活，锁存和输出触发控制信号。

公开(公告)号：US20120188836A1

公开(公告)日：2012-07-26

申请号：US13356771

申请日：2012-01-24

Applicant: Kang Seol LEE ,  Tae Sik YUN

Inventor： Kang Seol LEE ,  Tae Sik YUN

IPC: G11C7/12 ,  G11C7/06

CPC classification number: G11C11/4091 ,  G11C11/4094

Abstract: A semiconductor memory apparatus includes a bit line sense amplifier unit and a driving voltage supply unit. The bit line sense amplifier unit senses and amplifies a signal provided from a memory cell using a pull-up driving voltage provided through a pull-up power line and a pull-down driving voltage provided through a pull-down power line. The driving voltage supply unit supplies the pull-down driving voltage having a first pull-down driving force during a first amplification period, and supplies the pull-down driving voltage having a second pull-down driving force greater than the first pull-down driving force during a second amplification period after the first amplification period.

Abstract translation: 半导体存储装置包括位线读出放大器单元和驱动电压提供单元。 位线读出放大器单元使用通过上拉电源线提供的上拉驱动电压和通过下拉电力线提供的下拉驱动电压来感测和放大从存储单元提供的信号。 驱动电压供应单元在第一放大期间提供具有第一下拉驱动力的下拉驱动电压，并且提供具有大于第一下拉驱动的第二下拉驱动力的下拉驱动电压 在第一扩增期后的第二扩增期间的力。

公开(公告)号：US07977966B2

公开(公告)日：2011-07-12

申请号：US11528643

申请日：2006-09-28

Applicant: Kang-Seol Lee ,  Seok-Cheol Yoon

Inventor： Kang-Seol Lee ,  Seok-Cheol Yoon

IPC: H03K19/00

CPC classification number: G05F1/465 ,  G11C5/147 ,  G11C29/06 ,  G11C29/12005

Abstract: An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generating circuit produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response to a test operation signal activated in a test operation. Accordingly, dropping of the internal voltage in the standby section of the test operation and failure due to open or short circuiting are prevented. As a result, reliability of the semiconductor chip, by preventing the generation of latch-up caused by breakdown of internal circuits, is assured.

Abstract translation: 内部电压产生电路用于对半导体器件执行TDBI（老化测试）操作。 内部电压产生电路在测试操作中响应于激活的测试操作信号，在不仅备用部分而且在有效部分中产生作为内部电压的高电压电平的内部电压。 因此，防止了测试操作的待机部分中的内部电压的下降以及由于开路或短路引起的故障。 结果，确保了通过防止由内部电路的击穿引起的闩锁而产生的半导体芯片的可靠性。

公开(公告)号：US07889574B2

公开(公告)日：2011-02-15

申请号：US12219572

申请日：2008-07-24

Applicant: Sang-Jin Byeon ,  Kang-Seol Lee

Inventor： Sang-Jin Byeon ,  Kang-Seol Lee

IPC: G11C7/10

CPC classification number: G11C7/12 ,  G11C7/06

Abstract: A semiconductor memory device employs a clamp for preventing latch up. For the purpose, the semiconductor memory device includes a precharging/equalizing unit for precharging and equalizing a pair of bit lines, and a control signal generating unit for producing a control signal which controls enable and disable of the precharging/equalizing unit, wherein the control signal generating unit includes a clamping unit to clamp its source voltage to a voltage level lower than that of its bulk bias.

Abstract translation: 半导体存储器件采用夹具来防止闩锁。 为此，半导体存储器件包括用于对一对位线进行预充电和均衡的预充电/均衡单元，以及用于产生控制预充电/均衡单元的使能和禁能的控制信号的控制信号产生单元，其中控制 信号发生单元包括钳位单元，用于将其源极电压钳位到低于其体积偏压的电压电平。

公开(公告)号：US20100232239A1

公开(公告)日：2010-09-16

申请号：US12493734

申请日：2009-06-29

Applicant: Tae Sik Yun ,  Kang Seol Lee

Inventor： Tae Sik Yun ,  Kang Seol Lee

IPC: G11C7/00

CPC classification number: G11C8/18

Abstract: A semiconductor memory apparatus includes a row path activating unit configured to generate a line connection control signal according to a received address and active command. The semiconductor memory apparatus also includes a cell array circuit unit including an input/output line switch for connecting a first input/output line in a cell block and a second input/output line extending to the outside of the cell block. The cell array also including a bit line switch for connecting a bit line pair to each other. The input/output line switch and the bit line switch are further controlled by the line connection control signal from the row path activating unit.

Abstract translation: 一种半导体存储装置，包括：行路径激活部，被配置为根据接收到的地址和主动命令生成线路连接控制信号。 半导体存储装置还包括一个单元阵列电路单元，包括用于连接单元块中的第一输入/输出线和延伸到单元块外部的第二输入/输出线的输入/输出线开关。 单元阵列还包括用于将位线对彼此连接的位线开关。 输入/输出线路开关和位线开关进一步由来自行路径激活单元的线路连接控制信号控制。