公开(公告)号：US20070040604A1

公开(公告)日：2007-02-22

申请号：US11209914

申请日：2005-08-22

申请人： Kanyu Cao ,  Yiping Fan ,  Hongyu Li ,  Chieh-Yuan Chao

发明人： Kanyu Cao ,  Yiping Fan ,  Hongyu Li ,  Chieh-Yuan Chao

IPC分类号： H03K5/00

CPC分类号： H03H11/22 ,  H03H2007/0192 ,  H03H2011/0494

摘要： The present invention provides methods and apparatuses for a polyphase filter, comprising: a first and second cascoded differential amplifiers configured to receive a first and second differential signals, the first cascoded differential amplifier having a first resistor coupled between current legs of the first cascoded differential amplifier and the second cascoded differential amplifier having a first capacitor coupled between current legs of the second cascoded differential amplifier; and a third and fourth cascoded differential amplifiers configured to receive said first and said second differential signals, the third cascoded differential amplifier having a second resistor coupled between current legs of the third cascoded differential amplifier and the fourth cascoded differential amplifier having a second capacitor coupled between current legs of the fourth cascoded differential amplifier; wherein the first and second cascoded differential amplifiers are configured to provide a first differential output in response to the first and second differential signals and the third and fourth cascoded differential amplifiers are configured to provide a second differential output in response to the first and second differential signals.

公开(公告)号：US07408395B2

公开(公告)日：2008-08-05

申请号：US10428444

申请日：2003-05-01

申请人： Kanyu Cao ,  Yiping Fan ,  Hongyu Li ,  Chieh-Yuan Chao

发明人： Kanyu Cao ,  Yiping Fan ,  Hongyu Li ,  Chieh-Yuan Chao

IPC分类号： H03L5/00

CPC分类号： H04L25/0296

摘要： Fast settling circuits and methods designed to align input signal amplitude level and to remove DC offset voltages with minimal loss of low frequency signal in receiving analog circuits are disclosed. With the key innovative circuits and methods for signal peak alignment, the disclosed circuits and methods achieve fast settling without significant attenuation of the input signal. Peak aligning circuits and methods can be implemented along with conventional RC AC coupling circuits. In applying the aligning circuits and methods to differential signal pair, DC offsets can be easily removed.

摘要翻译： 公开了用于调整输入信号幅度电平的快速稳定电路和方法，并且在接收模拟电路中以最小的低频信号损失去除DC偏移电压。 利用用于信号峰对准的关键创新电路和方法，所公开的电路和方法实现快速建立，而没有输入信号的显着衰减。 峰值对准电路和方法可以与传统的RC AC耦合电路一起实现。 在将对准电路和方法应用于差分信号对时，可以容易地去除直流偏移。

公开(公告)号：US06784727B1

公开(公告)日：2004-08-31

申请号：US10443178

申请日：2003-05-21

申请人： Kanyu Cao ,  Tung-Shan Chen ,  Hongyu Li ,  Chieh-Yuan Chao

发明人： Kanyu Cao ,  Tung-Shan Chen ,  Hongyu Li ,  Chieh-Yuan Chao

IPC分类号： H03B100

CPC分类号： H04B1/30 ,  H03D2200/0047

摘要： A fast-setting DC offset removal circuit with continuous cutoff frequency switching is disclosed. In the preferred embodiment, the circuit is implemented using a pair of RC filters for receiving a differential signal pair and a continuous, variable resistance control circuit. The control circuit can be current-controlled or voltage controlled to provide fast settling of the received signal and the removal of the DC offset components. Additionally, by using a current-controlled control circuit, the cutoff frequency of the RC filter can be ramped from high to low in a continuous manner, thereby minimizing the generation of DC offsets.

摘要翻译： 公开了具有连续截止频率切换的快速设置DC偏移去除电路。 在优选实施例中，使用一对用于接收差分信号对的RC滤波器和连续的可变电阻控制电路来实现该电路。 控制电路可以是电流控制或电压控制，以提供接收信号的快速建立和DC偏移分量的去除。 此外，通过使用电流控制控制电路，RC滤波器的截止频率可以从高到低以连续的方式斜坡化，从而最小化DC偏移的产生。

公开(公告)号：US08595538B2

公开(公告)日：2013-11-26

申请号：US12041543

申请日：2008-03-03

申请人： Yifeng Zhang ,  Peiqi Xuan ,  Kanyu Cao ,  Xiaodong Jin

发明人： Yifeng Zhang ,  Peiqi Xuan ,  Kanyu Cao ,  Xiaodong Jin

IPC分类号： G06F1/00 ,  G06F1/04 ,  H03L7/06

CPC分类号： H03L7/099 ,  H03L2207/12

摘要： In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a reference frequency and operative to generate a single clock frequency and a clock signal quadrature output frequency and a clock signal in-phase output with the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency being a fraction of the frequency of the single clock frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output, the final output of the plurality of dividers being synchronized to the reference frequency.

摘要翻译： 在本发明的实施例中，公开了一种时钟发生器电路，其包括响应于参考频率并且可操作以产生单个时钟频率和时钟信号正交输出频率的锁相环（PLL）和时钟信号 相位输出与时钟信号的频率正交输出频率和时钟信号同相输出频率是单个时钟频率频率的一部分。 PLL包括产生单个时钟频率的单个压控振荡器（VCO）。 多个分频器被包括在时钟发生器电路中，并且响应于时钟信号正交输出频率和时钟信号同相输出频率，并且产生多个时钟频率，每个时钟频率是唯一的频率，每个分频器 产生输出，多个分频器的最终输出与参考频率同步。