公开(公告)号：US20190012155A1

公开(公告)日：2019-01-10

申请号：US16108888

申请日：2018-08-22

Applicant: Karlsruhe Institute of Technology

Inventor： Oliver Oey ,  Timo Stripf ,  Michael Rückauer ,  Jürgen Becker

IPC: G06F8/41 ,  G06F8/60

Abstract: A compiler system, method and computer program product for optimizing a program is disclosed. The compiler includes an extractor module configured to extract, from an initial program code, a hierarchical task representation wherein each node of the hierarchical task representation corresponds to a potential unit of execution. The root node of the hierarchical task representation represents the entire initial program code and each child node represents a sub-set of units of execution of its respective parent node. It further has a parallelizer module configured to apply to the hierarchical task representation pre-defined parallelization rules associated with the processing device to automatically adjust the hierarchical task representation by assigning particular units of execution to particular processing units of the processing device and by inserting communication and/or synchronization in that the adjusted hierarchical task representation reflects parallel program code for the processing device.

公开(公告)号：US10592219B2

公开(公告)日：2020-03-17

申请号：US16108888

申请日：2018-08-22

Applicant: Karlsruhe Institute of Technology

Inventor： Oliver Oey ,  Timo Stripf ,  Michael Rückauer ,  Jürgen Becker

IPC: G06F9/46 ,  G06F9/44 ,  G06F9/50 ,  G06F17/50 ,  G06F8/41 ,  G06F8/60 ,  G06F9/48 ,  G06F8/72

Abstract: A compiler system, method and computer program product for optimizing a program is disclosed. The compiler includes an extractor module configured to extract, from an initial program code, a hierarchical task representation wherein each node of the hierarchical task representation corresponds to a potential unit of execution. The root node of the hierarchical task representation represents the entire initial program code and each child node represents a sub-set of units of execution of its respective parent node. It further has a parallelizer module configured to apply to the hierarchical task representation pre-defined parallelization rules associated with the processing device to automatically adjust the hierarchical task representation by assigning particular units of execution to particular processing units of the processing device and by inserting communication and/or synchronization in that the adjusted hierarchical task representation reflects parallel program code for the processing device.