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公开(公告)号：US20180143813A1
公开(公告)日：2018-05-24
申请号：US15875553
申请日：2018-01-19
Applicant: Karlsruhe Institute of Technology
Inventor： Johannes Meyer , Oliver Oey , Timo Stripf , Jürgen Becker
IPC: G06F8/41
CPC classification number: G06F8/443 , G06F8/433 , G06F8/4432 , G06F8/4434 , G06F8/4441 , G06F8/456 , G06F8/457 , G06F8/52 , G06F9/445
Abstract: A compiler system, computer-implemented method and computer program product for optimizing a program for multi-processor system execution. The compiler includes an interface component configured to load from a storage component program code to be executed by one or more processors (P1 to Pn) of a multi-processor system. The compiler further includes a static analysis component configured to determine data dependencies) within the program code, and further determines all basic blocks of the control flow graph providing potential insertion positions along paths where communication statements can be inserted to enable data flow between different processors at runtime. An evaluation function component of the compiler is configured to evaluate each potential insertion position with regards to its impact on program execution on the multi-processor system at runtime by using a predefined execution evaluation function.
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公开(公告)号：US20190012155A1
公开(公告)日：2019-01-10
申请号：US16108888
申请日：2018-08-22
Applicant: Karlsruhe Institute of Technology
Inventor： Oliver Oey , Timo Stripf , Michael Rückauer , Jürgen Becker
Abstract: A compiler system, method and computer program product for optimizing a program is disclosed. The compiler includes an extractor module configured to extract, from an initial program code, a hierarchical task representation wherein each node of the hierarchical task representation corresponds to a potential unit of execution. The root node of the hierarchical task representation represents the entire initial program code and each child node represents a sub-set of units of execution of its respective parent node. It further has a parallelizer module configured to apply to the hierarchical task representation pre-defined parallelization rules associated with the processing device to automatically adjust the hierarchical task representation by assigning particular units of execution to particular processing units of the processing device and by inserting communication and/or synchronization in that the adjusted hierarchical task representation reflects parallel program code for the processing device.
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公开(公告)号：US10592219B2
公开(公告)日：2020-03-17
申请号：US16108888
申请日：2018-08-22
Applicant: Karlsruhe Institute of Technology
Inventor： Oliver Oey , Timo Stripf , Michael Rückauer , Jürgen Becker
Abstract: A compiler system, method and computer program product for optimizing a program is disclosed. The compiler includes an extractor module configured to extract, from an initial program code, a hierarchical task representation wherein each node of the hierarchical task representation corresponds to a potential unit of execution. The root node of the hierarchical task representation represents the entire initial program code and each child node represents a sub-set of units of execution of its respective parent node. It further has a parallelizer module configured to apply to the hierarchical task representation pre-defined parallelization rules associated with the processing device to automatically adjust the hierarchical task representation by assigning particular units of execution to particular processing units of the processing device and by inserting communication and/or synchronization in that the adjusted hierarchical task representation reflects parallel program code for the processing device.
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公开(公告)号：US10564947B2
公开(公告)日：2020-02-18
申请号：US15875553
申请日：2018-01-19
Applicant: Karlsruhe Institute of Technology
Inventor： Johannes Meyer , Oliver Oey , Timo Stripf , Jürgen Becker
Abstract: A compiler system, computer-implemented method and computer program product for optimizing a program for multi-processor system execution. The compiler includes an interface component configured to load from a storage component program code to be executed by one or more processors (P1 to Pn) of a multi-processor system. The compiler further includes a static analysis component configured to determine data dependencies) within the program code, and further determines all basic blocks of the control flow graph providing potential insertion positions along paths where communication statements can be inserted to enable data flow between different processors at runtime. An evaluation function component of the compiler is configured to evaluate each potential insertion position with regards to its impact on program execution on the multi-processor system at runtime by using a predefined execution evaluation function.
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