-
1.发明申请HIGH-SPEED FREQUENCY DIVIDER AND A PHASE LOCKED LOOP THAT USES THE HIGH-SPEED FREQUENCY DIVIDER 有权高速频率分频器和使用高速频率分路器的相位锁定环路公开(公告)号：US20120032715A1
公开(公告)日：2012-02-09
申请号：US12852520
申请日：2010-08-09
申请人： Karthik Subburaj , Dhanya K
发明人： Karthik Subburaj , Dhanya K
CPC分类号： H03L7/18 , H03K23/667 , H03L2207/50
摘要： A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise.
摘要翻译： 分频器包括最低有效（LS）级，多级联分频级和输出级。 LS级接收输入信号，程序位和第一模式信号，并产生第一分频信号和输出模式信号。 多个除法器级中的每一个将前一级的输出的频率除以由相应的程序位和对应的模式信号指定的值。 多个除法器级中的第一除法器级被耦合以接收第一分频信号并产生第一模式信号。 输出级接收输出模式信号和控制信号，并且如果控制信号处于一个逻辑电平，则通过将输出模式信号的频率除以2来产生输出信号。 输出级转换输出模式信号，否则不进行除法。
-
2.发明授权公开(公告)号：US08248118B2
公开(公告)日：2012-08-21
申请号：US12852520
申请日：2010-08-09
申请人： Karthik Subburaj , Dhanya K
发明人： Karthik Subburaj , Dhanya K
CPC分类号： H03L7/18 , H03K23/667 , H03L2207/50
摘要： A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise.
-
3.发明申请HIGH-SPEED FREQUENCY DRIVER AND A PHASE LOCKED LOOP THAT USES THE HIGH-SPEED FREQUENCY DIVIDER 有权高速频率驱动器和使用高速频率分路器的相位锁定环路公开(公告)号：US20120194235A1
公开(公告)日：2012-08-02
申请号：US13425167
申请日：2012-03-20
申请人： Karthik Subburaj , Dhanya K
发明人： Karthik Subburaj , Dhanya K
IPC分类号： H03L7/08
CPC分类号： H03L7/18 , H03K23/667 , H03L2207/50
摘要： A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise.
摘要翻译： 分频器包括最低有效（LS）级，多级联分频级和输出级。 LS级接收输入信号，程序位和第一模式信号，并产生第一分频信号和输出模式信号。 多个除法器级中的每一个将前一级的输出的频率除以由相应的程序位和对应的模式信号指定的值。 多个除法器级中的第一除法器级被耦合以接收第一分频信号并产生第一模式信号。 输出级接收输出模式信号和控制信号，并且如果控制信号处于一个逻辑电平，则通过将输出模式信号的频率除以2来产生输出信号。 输出级转换输出模式信号，否则不进行除法。
-
-
搜索结果
3 条记录 (耗时 0.011 秒)
