公开(公告)号：US06339229B1

公开(公告)日：2002-01-15

申请号：US09531523

申请日：2000-03-21

申请人： Katsuya Shiga ,  Naofumi Murata

发明人： Katsuya Shiga ,  Naofumi Murata

IPC分类号： H01L2166

CPC分类号： H01L22/34 ,  G01N27/92 ,  G01R31/2642 ,  G01R31/2648 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test structure for insulation-film evaluation has a CCD structure comprising a semiconductor substrate (1), a gate insulating film (2) to be evaluated which is formed across the main surface of the semiconductor substrate (1), a plurality of gate electrodes (3a-3i) equally spaced in this order on the gate insulating film (2), a wire (20) connected to the gate electrodes (3a, 3d, 3g), a wire (21) connected to the gate electrodes (3b, 3e, 3h), and a wire (22) connected to the gate electrodes (3c, 3f, 3i). The test structure further comprises a read circuit (5) including an inverter (4) and other elements connected to the output stage of the CCD structure. This test structure allows simple failure location.

摘要翻译： 用于绝缘膜评估的测试结构具有包括半导体衬底（1），横跨半导体衬底（1）的主表面形成的待评估的栅极绝缘膜（2）的CCD结构，多个栅电极 （3a-3d），栅极绝缘膜（2）上依次等间隔地连接到栅电极（3a，3d，3g）上的导线（20），连接到栅电极（3b， 3e，3h）和连接到栅电极（3c，3f，3i）的导线（22）。 测试结构还包括读取电路（5），其包括逆变器（4）和连接到CCD结构的输出级的其它元件。 该测试结构允许简单的故障定位。

公开(公告)号：US6127837A

公开(公告)日：2000-10-03

申请号：US466932

申请日：1999-12-20

申请人： Shigehisa Yamamoto ,  Katsuya Shiga

发明人： Shigehisa Yamamoto ,  Katsuya Shiga

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L21/66 ,  G01R31/00

CPC分类号： G01R31/318505 ,  G01R31/2886 ,  G01R31/318511 ,  G01R31/2856

摘要： A semiconductor device testing method using a semiconductor device testing apparatus that can improve the contact characteristic between probe needles and power-supply terminals and signal terminals while ensuring efficiency of product utilization of a tested wafer. Provided on a probe wafer (4) are bumps (5) formed in the same positions in mirror symmetry as the positions of pads (3) formed in individual chips (2) on a tested wafer (1), a common interconnection (6) for interconnecting bumps (5) to be supplied with the same power supplies and signals, and terminals (7) connected to the common interconnection (6) to supply power supplies and signals to the common interconnection (6) from the outside. The bumps (5) come in contact with the pads (3) in the chips (2) when the probe wafer (4) and the tested wafer (1) are put together. The common interconnection (6) supplies the power supplies and signals for a burn-in test to the pads (3) in the chips (2).

摘要翻译： 一种使用半导体器件测试装置的半导体器件测试方法，其可以在确保测试晶片的产品利用效率的同时，提高探针与电源端子和信号端子之间的接触特性。 提供在探针晶片（4）上的凸起（5）是与形成在测试晶片（1）上的各个芯片（2）中的焊盘（3）的位置成反射对称的相同位置的凸块（5），公共互连（6） 用于互连凸起（5）以提供相同的电源和信号;以及连接到公共互连（6）的端子（7），以从外部向公共互连（6）提供电源和信号。 当探针晶片（4）和测试晶片（1）放在一起时，凸起（5）与芯片（2）中的焊盘（3）接触。 公共互连（6）为芯片（2）中的焊盘（3）提供用于老化测试的电源和信号。

公开(公告)号：US6037794A

公开(公告)日：2000-03-14

申请号：US129699

申请日：1998-08-05

申请人： Shigehisa Yamamoto ,  Katsuya Shiga

发明人： Shigehisa Yamamoto ,  Katsuya Shiga

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L21/66 ,  G01R31/02

CPC分类号： G01R31/318505 ,  G01R31/2886 ,  G01R31/318511 ,  G01R31/2856

摘要： An object is to obtain a semiconductor device testing apparatus that can improve the contact characteristic between probe needles and power-supply terminals and signal terminals while ensuring efficiency of product utilization of a tested wafer. Provided on a probe wafer (4) are bumps (5) formed in the same positions in mirror symmetry as the positions of pads (3) formed in individual chips (2) on a tested wafer (1), a common interconnection (6) for interconnecting bumps (5) to be supplied with the same power supplies and signals, and terminals (7) connected to the common interconnection (6) to supply power supplies and signals to the common interconnection (6) from the outside. The bumps (5) come in contact with the pads (3) in the chips (2) when the probe wafer (4) and the tested wafer (1) are put together. The common interconnection (6) supplies the power supplies and signals for a burn-in test to the pads (3) in the chips (2).

摘要翻译： 本发明的目的是获得能够提高探针和电源端子与信号端子之间的接触特性的半导体器件测试装置，同时确保测试晶片的产品利用效率。 提供在探针晶片（4）上的凸起（5）是与形成在测试晶片（1）上的各个芯片（2）中的焊盘（3）的位置成反射对称的相同位置的凸块（5），公共互连（6） 用于互连凸起（5）以提供相同的电源和信号;以及连接到公共互连（6）的端子（7），以从外部向公共互连（6）提供电源和信号。 当探针晶片（4）和测试晶片（1）放在一起时，凸块（5）与芯片（2）中的焊盘（3）接触。 公共互连（6）为芯片（2）中的焊盘（3）提供用于老化测试的电源和信号。