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公开(公告)号：US06363063B1
公开(公告)日：2002-03-26
申请号：US09047824
申请日：1998-03-25
IPC分类号： H04B700
CPC分类号： H03J1/0066 , H04H20/22 , H04H60/37 , H04H2201/13
摘要： A receiver receives FM multiplex broadcast data of both RDS and DARC systems by using one front end. A BIC detection circuit (101) detects a block identification code (BIC) included in received data. A coincidence/non-coincidence detection circuit (104) judges whether or not a BIC detection timing is correct and emits a coincidence/non-coincidence pulse. A forward protection circuit (106) counts a frequency of outputs of non-coincidence pulses and retains an established synchronous condition until the counted value exceeds a predetermined value. Then, a forward protection control circuit (108) inhibits the forward protection circuit from performing a count operation while a search is performed for selecting a station. Also, a rearward protection circuit (105) counts a frequency of outputs of coincidence pulses and establishes a synchronous condition when the counted value reaches a predetermined value. Further, a rearward protection control circuit (800) inhibits the rearward protection circuit from performing a count operation while a search is performed.
摘要翻译： 接收机通过使用一个前端接收RDS和DARC系统的FM多路复用广播数据。 BIC检测电路（101）检测包含在接收数据中的块识别码（BIC）。 一致/不符合检测电路（104）判断BIC检测定时是否正确并且发出一致/非重合脉冲。 正向保护电路（106）对不一致脉冲的输出频率进行计数，并保持建立的同步状态，直到计数值超过预定值。 然后，当进行用于选择站的搜索时，前向保护控制电路（108）禁止前向保护电路执行计数操作。 此外，后方保护电路（105）对一致脉冲的输出频率进行计数，并且当计数值达到预定值时建立同步状态。 此外，在执行搜索时，后向保护控制电路（800）禁止后向保护电路执行计数操作。
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公开(公告)号：US5752176A
公开(公告)日：1998-05-12
申请号：US624739
申请日：1996-03-26
申请人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
发明人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
CPC分类号： H04B1/1646 , H04H20/26 , H04H20/30 , H04H20/22 , H04H2201/15
摘要： An SI judging circuit in a service detecting section detects a service identification code included in a block included in received superimposed FM data. When the block represents an unnecessary service, the SI judging circuit generates a predetermined service detecting signal, which is supplied to a station selecting microcomputer. A user operates a station selecting key to request the change of the broadcasting station. When the change is requested, and also the service detecting signal indicating that the service included in the received block is not needed is supplied to the station selecting microcomputer by the SI judging circuit, a control section of the station selecting microcomputer outputs station data corresponding to the requested station to a PLL synthesizer, and then the frequency signal (tuning frequency) is changed at a front end. This enables data received during a period for receiving blocks for unnecessary services to be NG, and can prevent data of blocks including necessary services from being NG.
摘要翻译： 服务检测部分中的SI判断电路检测包含在接收到的叠加FM数据中的块中的服务识别码。 当该块表示不必要的服务时，SI判断电路产生预定的服务检测信号，该信号被提供给站选择微计算机。 用户操作站选择键以请求改变广播电台。 当请求改变，并且指示包含在接收块中的服务不需要的服务检测信号通过SI判断电路提供给站选择微计算机时，站选择微机的控制部分输出对应于 所请求的站到PLL合成器，然后在前端改变频率信号（调谐频率）。 这使得在用于接收不必要服务的块的周期期间接收的数据为NG，并且可以防止包括必需服务的块的数据成为NG。
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3.发明授权FM multiplex broadcast receiving circuit for detecting presence or absence of multiplex information 失效FM多路复用广播接收电路，用于检测多路复用信息的存在或不存在
公开(公告)号：US5802067A
公开(公告)日：1998-09-01
申请号：US614466
申请日：1996-03-12
申请人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
发明人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
CPC分类号： H04H20/34 , H04H40/18 , H04H2201/13
摘要： In accordance with the operation of an operating section 14, a control section 12 performs a reception control operation and demodulates a signal passing through a band pass filter 7 for extracting a multiplex signal using a multiplex signal demodulating section 8 when receiving a broadcast signal. A block synchronization circuit 16 of a synchronization circuit 9 carries out block synchronization processing on the demodulated signal. When block synchronization is established, a synchronization determination signal is supplied to a detecting section DET and the detecting section DET determines that a broadcasting station whose radio waves are currently being received is a multiplex broadcasting station.
摘要翻译： 根据操作部分14的操作，控制部分12在接收广播信号时，执行接收控制操作并且解调通过带通滤波器7的信号，以使用多路复用信号解调部分8提取多路复用信号。 同步电路9的块同步电路16对解调信号执行块同步处理。 当建立块同步时，将同步确定信号提供给检测部分DET，并且检测部分DET确定当前正在接收无线电波的广播电台是多路复用广播电台。
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4.发明授权Digital signal processing for controlling error correction based on the state of the control bit 失效数字信号处理，用于根据控制位的状态控制纠错
公开(公告)号：US5757825A
公开(公告)日：1998-05-26
申请号：US588639
申请日：1996-01-19
申请人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
发明人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
CPC分类号： H04L1/0065 , H04L1/0057 , H04L1/0061
摘要： In multiplex FM broadcasting, a digital signal is composed of a frame which consists of a predetermined number of blocks in the vertical direction, a block consisting of a predetermined number of bits in the horizontal direction and having a horizontal parity (error correcting code) for correcting errors in the horizontal direction and a vertical parity for correcting errors in the vertical direction. The block also has a control bit for determining whether the error correction in the horizontal direction is to be carried out only once. A decoding identification detector (20) detects the content of the control bit, a controller (12) controls the re-writing of the digital signal into a frame buffer (13) after the error correction of the digital signal in the vertical direction by an error corrector (14). The controller (12) also controls the provision of the digital signal stored in the buffer (13) to the error corrector (14) according to the content of the control bit, determining whether the second error correction in the horizontal direction is to be carried out.
摘要翻译： 在多路复用FM广播中，数字信号由在垂直方向上由预定数量的块组成的帧构成，由水平方向上的预定数量的比特组成的块，并且具有水平奇偶校验码（纠错码） 校正水平方向上的误差和用于校正垂直方向上的误差的垂直奇偶校验。 该块还具有用于确定水平方向上的纠错是否仅被执行一次的控制位。 解码识别检测器（20）检测控制位的内容，控制器（12）在垂直方向的数字信号的纠错之后控制数字信号重新写入帧缓冲器（13） 误差校正器（14）。 控制器（12）还根据控制位的内容控制向缓冲器（13）中存储的数字信号的提供给纠错器（14），确定是否要携带水平方向上的第二纠错 出来
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公开(公告)号：US5960328A
公开(公告)日：1999-09-28
申请号：US622048
申请日：1996-03-26
申请人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
发明人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
IPC分类号： H04B1/16
CPC分类号： H04H20/26 , H04B1/1646 , H04H20/34 , H04H20/22 , H04H2201/15
摘要： Superimposed FM data is demodulated to digital data. A synchronism reproducing circuit (data block detecting section) detects the front of blocks in the digital data to generate a block head signal (a station change timing signal), which is supplied to a control section of a station selecting microcomputer. When a station selecting key requests a change of the received station, station data corresponding to a requested station is supplied to the control section (a station selecting control section). When the block head signal is inputted after requesting the change of the station, the control section begins to output station change data to a PLL frequency synthesizer in order to change the frequency signal in a front end. This prevents a latter part of a block in received superimposed FM data from being NG data.
摘要翻译： 叠加的FM数据被解调为数字数据。 同步再现电路（数据块检测部分）检测数字数据中的块的前端以产生提供给站选择微计算机的控制部分的块头信号（站改变定时信号）。 当站选择键请求改变接收站时，与所请求站对应的站数据被提供给控制区（站选择控制区）。 当在请求改变站之后输入块头信号时，控制部分开始向PLL频率合成器输出站改变数据，以改变前端的频率信号。 这防止接收到的叠加的FM数据中的块的后半部分成为NG数据。
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公开(公告)号：US5825888A
公开(公告)日：1998-10-20
申请号：US712123
申请日：1996-09-11
IPC分类号： H04L9/16 , H04B1/16 , H04H20/00 , H04H20/62 , H04H60/15 , H04H60/23 , H04L9/18 , H04L9/20 , H04L29/06 , H04L9/00
CPC分类号： H04L63/04 , H04B1/707 , H04H20/62 , H04H60/15 , H04H60/16 , H04H60/23 , H04L25/03866 , H04L29/06
摘要： In a packet analyzing circuit, first and second key data are detected and stored in respective first and second key data registers. First and second key generation circuits generate first and second keys from the first and second key data. An exclusive OR operation is carried out to both keys so as to generate a scrambling key. Using the scrambling key as an initial value, a random number generator generates a PN code used for scrambling, so that scrambled data is descrambled by adding the PN code to the data. The first key generation circuit, which receives a control signal CON from a timing generation circuit, is controlled by the control signal CON such that a scrambling key is generated only when the random number generator needs an initial value.
摘要翻译： 在分组分析电路中，第一和第二密钥数据被检测并存储在相应的第一和第二密钥数据寄存器中。 第一和第二密钥生成电路从第一和第二密钥数据生成第一和第二密钥。 对两个密钥执行异或操作，以产生加扰密钥。 使用加扰密钥作为初始值，随机数生成器生成用于加扰的PN码，从而通过将PN码添加到数据来对加扰数据进行解扰。 从定时发生电路接收控制信号CON的第一密钥生成电路由控制信号CON控制，使得仅当随机数发生器需要初始值时才产生加扰密钥。
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公开(公告)号：US5835499A
公开(公告)日：1998-11-10
申请号：US711852
申请日：1996-09-10
CPC分类号： H04L1/0057 , H04L25/03866
摘要： A scrambling key is generated from demodulated and error-corrected FM demodulation data for use in descrambling. During this process, if error correction has not been normally conducted to an object data packet, a subsequent descrambling operation is not executed to that data packet. In addition, a descrambling operation is not carried out if the object data packet is a parity packet.
摘要翻译： 从用于解扰的解调和纠错的FM解调数据产生加扰密钥。 在该过程中，如果对目标数据分组未正常进行纠错，则不对该数据分组执行后续的解扰操作。 此外，如果对象数据分组是奇偶分组，则不执行解扰操作。
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8.发明授权Digital signal receiver capable of receiving data encrypted and transmitted in online processing 失效数字信号接收机能够接收在线处理中加密和传输的数据
公开(公告)号：US5784462A
公开(公告)日：1998-07-21
申请号：US700773
申请日：1996-08-22
CPC分类号： H04H60/23 , H04L9/0897 , H04H60/27 , H04L2209/34 , H04L2209/80 , H04L7/04
摘要： In a decoding processing circuit of a digital signal receiver, a first comparison circuit detects that a prefix of packet data is inputted in a shift register on the basis of a count value of a counter circuit. In response to the result of detection, a pseudo-random binary sequence generation circuit outputs a pseudo-random binary sequence on the basis of a data group number and a data packet number outputted from the shift register and key data previously extracted by a key data fetch circuit. When a second comparison circuit detects that block data in the data packet is inputted in the shift register, an exclusive OR circuit exclusively ORs the pseudo-random binary sequence with receive data, so that decoded data is inputted in the shift register.
摘要翻译： 在数字信号接收机的解码处理电路中，第一比较电路基于计数器电路的计数值检测分组数据的前缀被输入到移位寄存器中。 响应于检测结果，伪随机二进制序列产生电路根据从移位寄存器输出的数据组号和数据分组号以及由密钥数据先前提取的密钥数据输出伪随机二进制序列 取电路。 当第二比较电路检测到数据分组中的块数据被输入到移位寄存器时，异或电路将伪随机二进制序列与接收数据专门进行OR运算，从而将解码数据输入到移位寄存器中。
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公开(公告)号：US6128390A
公开(公告)日：2000-10-03
申请号：US854602
申请日：1997-05-12
摘要： A second random number generator (102) sets a scramble key data included in a transmitted/received data to an initial value, and it generates predetermined second random numbers. A first random number generator (101) generates first random numbers from the second random numbers supplied by the second random number generator (102). The generation of the first random numbers by the first random number generator (101) is controlled by an output from a first control circuit (103). Since the output from the first control circuit (103) is changed in accordance with a service identification code SI, the first random numbers generated from the first random number generator (101) are changed. The first random numbers are input to a gate circuit (105) via a second control circuit (104). The second control circuit (104) inhibits the output of the first random numbers in accordance with the SI value. In such a manner, scrambling or descrambling is controlled in the gate circuit (105).
摘要翻译： 第二随机数生成器（102）将包含在发送/接收数据中的加扰密钥数据设置为初始值，并且生成预定的第二随机数。 第一随机数生成器（101）从由第二随机数发生器（102）提供的第二随机数生成第一随机数。 由第一随机数发生器（101）产生的第一随机数由第一控制电路（103）的输出控制。 由于根据服务识别码SI改变来自第一控制电路（103）的输出，所以从第一随机数发生器（101）产生的第一随机数改变。 第一随机数经由第二控制电路（104）输入到门电路（105）。 第二控制电路（104）根据SI值禁止第一随机数的输出。 以这种方式，在门电路（105）中控制加扰或解扰。
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