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公开(公告)号：US06281937B1
公开(公告)日：2001-08-28
申请号：US09269180
申请日：1999-05-04
IPC分类号： H04N544
CPC分类号： H04H60/25 , H04H20/55 , H04H2201/15
摘要： In a receiver in a data broadcasting system, a receiver in a second data broadcasting system according to the present invention is characterized by comprising judging device for judging whether or not program data constituting at least one of received programs has been updated, and switching device for switching, when it is judged by the judging device that the program data has been updated, a program to be displayed into the program whose program data updating has been performed.
摘要翻译： 在数据广播系统的接收机中，根据本发明的第二数据广播系统中的接收机的特征在于包括判断装置，用于判断构成至少一个所接收的节目的节目数据是否已被更新;以及切换装置， 当由判断装置判断出节目数据已被更新时，切换到要被执行节目数据更新的节目中的节目。
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公开(公告)号：US5719873A
公开(公告)日：1998-02-17
申请号：US499256
申请日：1995-07-07
申请人： Syugo Yamashita , Yoshikazu Tomida , Masayuki Takada , Toru Kuroda , Tadashi Isobe , Osamu Yamada
发明人： Syugo Yamashita , Yoshikazu Tomida , Masayuki Takada , Toru Kuroda , Tadashi Isobe , Osamu Yamada
CPC分类号： H04L7/08 , H04B7/2621 , H04J3/0608
摘要： A frame-synchronous reproducing circuit (10) includes a BIC status register (20) of six stages, and a BIC status signal (c) from each stage of the register is applied to a BIC pattern determination circuit (24) in which the BIC status signal (c) and a BIC changing pattern being stored in advance are compared with each other. If the both are coincident with each other, the BIC pattern determination circuit (24) applies a high-level signal to a JK flip-flop (26) via an OR circuit (48), whereby a high-level signal representing that frame synchronization has been settled is outputted from the JK flip-flop (26).
摘要翻译： 帧同步再现电路（10）包括六级的BIC状态寄存器（20），并且来自寄存器的每一级的BIC状态信号（c）被施加到BIC模式确定电路（24），其中BIC 将预先存储的状态信号（c）和BIC变更模式进行比较。 如果两者彼此一致，则BIC模式确定电路（24）经由OR电路（48）向JK触发器（26）施加高电平信号，由此表示该帧同步的高电平信号 已经稳定的是从JK触发器（26）输出的。
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公开(公告)号：US06260026B1
公开(公告)日：2001-07-10
申请号：US08900839
申请日：1997-07-25
申请人： Yoshikazu Tomida , Tatsuo Hiramatsu , Naruto Nishimura , Hironori Mitoh , Seiji Suzuki , Masahiro Sata , Masahiro Seto , Ryuuji Yoshihara , Hiromichi Suzuki , Tadashi Etoh
发明人： Yoshikazu Tomida , Tatsuo Hiramatsu , Naruto Nishimura , Hironori Mitoh , Seiji Suzuki , Masahiro Sata , Masahiro Seto , Ryuuji Yoshihara , Hiromichi Suzuki , Tadashi Etoh
IPC分类号： G06F1760
CPC分类号： G07F7/08 , G06Q20/04 , G06Q20/20 , G06Q20/204 , G06Q20/403 , G06Q40/025 , G07F7/1008
摘要： The credit card information management system checks the creditability of a credit card intended to be used for purchase of goods or service by using the card information owned by member stores of credit companies. A host computer of the card management center outputs information regarding the validity or invalidity of a credit card of a customer member of a credit company as card information, a transmission facility wirelessly transmits digital data of the card information. A receiving facility of a member store receives radio signals of the card information and checks whether or not there is any missing of data. If any missing occurs, a transfer of the missed data is requested to the host computer. A terminal computer extracts only the card information necessary for one's own store from the data outputted by the host computer and data outputted in response to the transfer request and stores the same in memory, and the terminal computer outputs judgement of validity or invalidity of a credit card inputted into a card reader.
摘要翻译： 信用卡信息管理系统通过使用信用公司会员商店所拥有的信用卡信息来检查旨在用于购买商品或服务的信用卡的可信度。 卡管理中心的主计算机输出有关信用卡客户成员的信用卡的有效性或无效信息作为卡信息，传输设备无线发送卡信息的数字数据。 成员商店的接收设施接收卡信息的无线电信号，并检查是否有数据丢失。 如果发生任何缺失，则向主计算机请求丢失数据的传输。 终端计算机仅从主计算机输出的数据中提取自己存储所需的卡信息，并根据转移请求输出数据，并将其存储在存储器中，终端计算机输出信用证的有效性或无效判定 卡输入到读卡器。
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4.发明授权Multiplexed digital signal receiving device capable of miniaturizing the configuration of a signal receiving portion 失效能够使信号接收部的结构小型化的复用数字信号接收装置
公开(公告)号：US5995517A
公开(公告)日：1999-11-30
申请号：US786338
申请日：1997-01-23
申请人： Yoshikazu Tomida , Hironori Mitoh , Masahiro Sata
发明人： Yoshikazu Tomida , Hironori Mitoh , Masahiro Sata
摘要： An FM multiplexed broadcasting signal received by an antenna and FM-demodulated by an FM tuner portion is demodulated by a demodulation LSI into a digital signal corresponding to packet data. The digital signal is successively supplied by every packet to a CPU of a receiving portion. The CPU of the receiving portion removes unnecessary data of the received data and then supplies only data required for a CPU of a personal computer via a buffer without delay from the reception. When a transferred packet is a successive reproduction program packet or a time information packet, the CPU of the personal computer calculates latency required before a predetermined data analysis processing is started, and performs data analysis processing in an elapse of the latency. Responsively, reconfiguration of program data is performed and corresponding character information or the like is output to a displaying portion.
摘要翻译： 由天线接收并由FM调谐器部分FM解调的FM多路复用广播信号由解调LSI解调为对应于分组数据的数字信号。 数字信号由每个包依次提供给接收部分的CPU。 接收部分的CPU删除接收到的数据的不必要的数据，然后从接收器不经延迟地仅经由缓冲器提供个人计算机的CPU所需的数据。 当传送的分组是连续的再现节目分组或时间信息分组时，个人计算机的CPU计算开始预定数据分析处理之前所需的等待时间，并且在等待时间过后进行数据分析处理。 响应地执行程序数据的重新配置，并将相应的字符信息等输出到显示部分。
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公开(公告)号：US5963452A
公开(公告)日：1999-10-05
申请号：US925641
申请日：1997-09-09
申请人： Tadashi Etoh , Yoshikazu Tomida , Tatsuo Hiramatsu , Hironori Mitoh , Masahiro Sata , Masahiro Seto , Ryuuji Yoshihara , Hiromichi Suzuki
发明人： Tadashi Etoh , Yoshikazu Tomida , Tatsuo Hiramatsu , Hironori Mitoh , Masahiro Sata , Masahiro Seto , Ryuuji Yoshihara , Hiromichi Suzuki
CPC分类号： G07F11/002 , G07F5/18 , G07F9/02
摘要： A system for managing sales of goods for vending machines includes a goods control center, a plurality of vending machines, and terminal computers equipped in the respective vending machines. The goods control center includes a host computer for preparing digital data signals as control instructions, and a frequency moderation sub-carrier broadcasting facility as a transmission facility for outputting the digital data signals. Each vending machine has a receiving facility for receiving the digital data signals from the goods control center, and a responding facility. Each terminal computer receives the digital data signals and selectively extracts the digital data as the control instructions necessary for the vending machine to thereby store the digital data necessary for the vending machine in a memory. Each terminal computer controls the vending machine on a basis of the control instructions stored in the memory, obtains goods market information of the vending machine, and outputs the goods market information to the responding facility for reporting the information to the host computer at the goods control center.
摘要翻译： 用于管理自动售货机的商品销售的系统包括货物控制中心，多台售货机以及配备在各自的售货机中的终端电脑。 货物控制中心包括用作准备作为控制指令的数字数据信号的主计算机，以及作为用于输出数字数据信号的传输设备的频率调节子载波广播设施。 每个售货机具有用于从商品控制中心接收数字数据信号的接收设备和响应设备。 每个终端计算机接收数字数据信号，并且选择性地提取数字数据作为自动售货机所需的控制指令，从而将自动售货机所需的数字数据存储在存储器中。 每个终端计算机根据存储在存储器中的控制指令来控制自动售货机，获得自动售货机的商品市场信息，并将货物市场信息输出到响应设施，以在货物控制下向主机报告信息 中央。
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公开(公告)号：US5652760A
公开(公告)日：1997-07-29
申请号：US554790
申请日：1995-11-07
IPC分类号： H04N19/00 , H04B1/16 , H04L1/00 , H04L1/24 , H04N7/20 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/65 , H04N19/70 , H04N19/89 , H04N21/61 , H04N21/647 , G06F11/00
摘要： An error rate measuring apparatus includes a demodulator, and data from the demodulator is applied to a decoding circuit in which an error bit number is evaluated for each of a BIC portion and a packet portion. In the BIC portion, if a synchronization is settled, the error bit number is evaluated by comparing received BICs and a predetermined BIC pattern, and if the synchronization is not settled, the error bit number is determined as eight (8) bits. In the packet portion, if a frame synchronization is settled and decoding is successful, the error bit number is calculated by comparing data before decoding and data after decoding with each other. If the frame synchronization is settled but the decoding is unsuccessful, a presumed error bit number is set according to the number of packets being decoded successfully in a first time horizontal direction, and if the frame synchronization is not settled, a predetermined error bit number is set. In each of the BIC portion and the packet portion, a bit error rate is calculated on the basis of the error bit number for each measurement range, and displayed on a monitor.
摘要翻译： 错误率测量装置包括解调器，并且来自解调器的数据被应用于对BIC部分和分组部分中的每一个评估错误比特数的解码电路。 在BIC部分中，如果同步被确定，则通过比较所接收的BIC和预定的BIC模式来评估错误比特数，并且如果同步未被确定，则错误比特数被确定为八（8）比特。 在分组部分中，如果帧同步被确定并且解码成功，则通过比较解码之前的数据和解码之后的数据来计算错误比特数。 如果帧同步被确定但是解码不成功，则根据在第一时间水平方向成功解码的分组的数量来设置推定的错误比特数，并且如果帧同步未被确定，则预定的错误比特数是 组。 在每个BIC部分和分组部分中，基于每个测量范围的误差位数来计算误码率，并显示在监视器上。
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公开(公告)号：US5825888A
公开(公告)日：1998-10-20
申请号：US712123
申请日：1996-09-11
IPC分类号： H04L9/16 , H04B1/16 , H04H20/00 , H04H20/62 , H04H60/15 , H04H60/23 , H04L9/18 , H04L9/20 , H04L29/06 , H04L9/00
CPC分类号： H04L63/04 , H04B1/707 , H04H20/62 , H04H60/15 , H04H60/16 , H04H60/23 , H04L25/03866 , H04L29/06
摘要： In a packet analyzing circuit, first and second key data are detected and stored in respective first and second key data registers. First and second key generation circuits generate first and second keys from the first and second key data. An exclusive OR operation is carried out to both keys so as to generate a scrambling key. Using the scrambling key as an initial value, a random number generator generates a PN code used for scrambling, so that scrambled data is descrambled by adding the PN code to the data. The first key generation circuit, which receives a control signal CON from a timing generation circuit, is controlled by the control signal CON such that a scrambling key is generated only when the random number generator needs an initial value.
摘要翻译： 在分组分析电路中，第一和第二密钥数据被检测并存储在相应的第一和第二密钥数据寄存器中。 第一和第二密钥生成电路从第一和第二密钥数据生成第一和第二密钥。 对两个密钥执行异或操作，以产生加扰密钥。 使用加扰密钥作为初始值，随机数生成器生成用于加扰的PN码，从而通过将PN码添加到数据来对加扰数据进行解扰。 从定时发生电路接收控制信号CON的第一密钥生成电路由控制信号CON控制，使得仅当随机数发生器需要初始值时才产生加扰密钥。
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8.发明授权FM multiplex broadcasting receiver and storage of received data in FM multiplex broadcasting receiver 失效FM复用广播接收机和接收数据的存储在FM多播广播接收机中公开(公告)号：US06594281B1
公开(公告)日：2003-07-15
申请号：US09308624
申请日：1999-05-25
IPC分类号： H04J100
CPC分类号： H04H60/27
摘要： A prefix corresponding to a data block at the head of each of data groups in data of a layer 3 of a received FM multiplex broadcast program and data of a layer 4 of the received FM multiplex broadcast program are stored in first storage means. When a data retention command is entered, the data of the layer 3 is produced on the basis of the prefix and the data of the layer 4 which are stored in the first storage means, and the produced data of the layer 3 is retained in second storage means as versatile recording and reproducing data.
摘要翻译： 在第一存储装置中存储与接收到的FM多路复用广播节目的层3的数据中的每个数据组的头部的数据块相对应的前缀和接收的FM多路复用广播节目的层4的数据的前缀。 当输入数据保留命令时，基于存储在第一存储装置中的第四层的前缀和数据产生层3的数据，并且将第三层的产生的数据保留在第二层 存储装置作为通用的记录和再现数据。
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公开(公告)号：US5912973A
公开(公告)日：1999-06-15
申请号：US623792
申请日：1996-03-29
IPC分类号： H04K1/02 , H04H20/00 , H04H20/28 , H04H20/55 , H04H60/15 , H04H60/23 , H04L9/22 , H04L9/24 , H04L9/06
摘要： An FM multiple radio broadcasting receiver includes a data group number and data packet number derivation circuit by which a data group number and a data packet number included in a prefix of FM subcarrier data are derived. A first random number generator generates a first random number on the basis of the data group number, the data packet number and scramble key data which is outputted from a scramble key generation circuit, and sets the first random number in a second random number generator as its initial value. Therefore, it is possible to appropriately scramble or descramble with using packet structure of the FM subcarrier data.
摘要翻译： FM多重无线电广播接收机包括数据组号和数据分组号导出电路，通过该数据组号和数据分组数导出电路，导出包含在FM子载波数据的前缀中的数据组号和数据分组号。 第一随机数生成器根据数据组号，数据分组号和加密密钥数据从密码产生电路输出，生成第一随机数，并将第二随机数生成器中的第一随机数设置为第二随机数生成器 其初始值。 因此，可以利用FM子载波数据的分组结构来适当地加扰或解扰。
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公开(公告)号：US5835499A
公开(公告)日：1998-11-10
申请号：US711852
申请日：1996-09-10
CPC分类号： H04L1/0057 , H04L25/03866
摘要： A scrambling key is generated from demodulated and error-corrected FM demodulation data for use in descrambling. During this process, if error correction has not been normally conducted to an object data packet, a subsequent descrambling operation is not executed to that data packet. In addition, a descrambling operation is not carried out if the object data packet is a parity packet.
摘要翻译： 从用于解扰的解调和纠错的FM解调数据产生加扰密钥。 在该过程中，如果对目标数据分组未正常进行纠错，则不对该数据分组执行后续的解扰操作。 此外，如果对象数据分组是奇偶分组，则不执行解扰操作。
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