公开(公告)号：US20080114821A1

公开(公告)日：2008-05-15

申请号：US11927927

申请日：2007-10-30

申请人： Takahiko MASUMOTO

发明人： Takahiko MASUMOTO

IPC分类号： G06F7/38

CPC分类号： H03H17/0664

摘要： A decimation filter has: a plurality of calculating devices each having a multiplier and an accumulator; a plurality of coefficient memories (a ring memory and shift registers) which store filter coefficients, and which correspond to the calculating devices, respectively; and a selector which sequentially selectively outputs the outputs of the plurality of calculating devices in synchronization with a clock signal. When a decimation ratio is n, filter coefficients which are sequentially shifted by an n number of filter coefficients are read out from the plurality of coefficient memories, and multiplied with a signal in the multipliers of the calculating devices, and results of the multiplications are accumulated in the accumulators to be output.

摘要翻译： 抽取滤波器具有：多个计算装置，每个具有乘法器和累加器; 存储滤波器系数的多个系数存储器（环形存储器和移位寄存器），分别对应于计算装置; 以及选择器，其与时钟信号同步地顺序地选择性地输出多个计算装置的输出。 当抽取比为n时，从多个系数存储器中读出顺序移位了n个滤波器系数的滤波器系数，并与计算装置的乘法器中的信号相乘，并且累加乘法结果 在蓄电池中输出。

公开(公告)号：US5802067A

公开(公告)日：1998-09-01

申请号：US614466

申请日：1996-03-12

申请人： Kazuhiro Kimura ,  Shigeaki Hayashibe ,  Yutaka Hirakoso ,  Takahiko Masumoto ,  Shizuka Ishimura ,  Toshiyuki Ozawa ,  Munehiro Suka

发明人： Kazuhiro Kimura ,  Shigeaki Hayashibe ,  Yutaka Hirakoso ,  Takahiko Masumoto ,  Shizuka Ishimura ,  Toshiyuki Ozawa ,  Munehiro Suka

IPC分类号： H04B1/16 ,  H04J3/12

CPC分类号： H04H20/34 ,  H04H40/18 ,  H04H2201/13

摘要： In accordance with the operation of an operating section 14, a control section 12 performs a reception control operation and demodulates a signal passing through a band pass filter 7 for extracting a multiplex signal using a multiplex signal demodulating section 8 when receiving a broadcast signal. A block synchronization circuit 16 of a synchronization circuit 9 carries out block synchronization processing on the demodulated signal. When block synchronization is established, a synchronization determination signal is supplied to a detecting section DET and the detecting section DET determines that a broadcasting station whose radio waves are currently being received is a multiplex broadcasting station.

摘要翻译： 根据操作部分14的操作，控制部分12在接收广播信号时，执行接收控制操作并且解调通过带通滤波器7的信号，以使用多路复用信号解调部分8提取多路复用信号。 同步电路9的块同步电路16对解调信号执行块同步处理。 当建立块同步时，将同步确定信号提供给检测部分DET，并且检测部分DET确定当前正在接收无线电波的广播电台是多路复用广播电台。

公开(公告)号：US5757825A

公开(公告)日：1998-05-26

申请号：US588639

申请日：1996-01-19

申请人： Kazuhiro Kimura ,  Shigeaki Hayashibe ,  Yutaka Hirakoso ,  Takahiko Masumoto ,  Shizuka Ishimura ,  Toshiyuki Ozawa ,  Munehiro Suka

发明人： Kazuhiro Kimura ,  Shigeaki Hayashibe ,  Yutaka Hirakoso ,  Takahiko Masumoto ,  Shizuka Ishimura ,  Toshiyuki Ozawa ,  Munehiro Suka

IPC分类号： H03M13/00 ,  H04L1/00 ,  F01B25/06

CPC分类号： H04L1/0065 ,  H04L1/0057 ,  H04L1/0061

摘要： In multiplex FM broadcasting, a digital signal is composed of a frame which consists of a predetermined number of blocks in the vertical direction, a block consisting of a predetermined number of bits in the horizontal direction and having a horizontal parity (error correcting code) for correcting errors in the horizontal direction and a vertical parity for correcting errors in the vertical direction. The block also has a control bit for determining whether the error correction in the horizontal direction is to be carried out only once. A decoding identification detector (20) detects the content of the control bit, a controller (12) controls the re-writing of the digital signal into a frame buffer (13) after the error correction of the digital signal in the vertical direction by an error corrector (14). The controller (12) also controls the provision of the digital signal stored in the buffer (13) to the error corrector (14) according to the content of the control bit, determining whether the second error correction in the horizontal direction is to be carried out.

摘要翻译： 在多路复用FM广播中，数字信号由在垂直方向上由预定数量的块组成的帧构成，由水平方向上的预定数量的比特组成的块，并且具有水平奇偶校验码（纠错码） 校正水平方向上的误差和用于校正垂直方向上的误差的垂直奇偶校验。 该块还具有用于确定水平方向上的纠错是否仅被执行一次的控制位。 解码识别检测器（20）检测控制位的内容，控制器（12）在垂直方向的数字信号的纠错之后控制数字信号重新写入帧缓冲器（13） 误差校正器（14）。 控制器（12）还根据控制位的内容控制向缓冲器（13）中存储的数字信号的提供给纠错器（14），确定是否要携带水平方向上的第二纠错 出来

公开(公告)号：US4882613A

公开(公告)日：1989-11-21

申请号：US259812

申请日：1988-10-19

申请人： Takahiko Masumoto

发明人： Takahiko Masumoto

IPC分类号： H04N9/64 ,  H04N11/24

CPC分类号： H04N11/006 ,  H04N9/646

摘要： A time compressed color difference signal included in a high definition television signal is roughly compensated for its units of an interval of one-half of a transmission sampling interval in a range obtained by multiplying the amount of a horizontal motion vector by a compression rate. In addition, the time compressed color difference signal roughly compensated for its finely compensated for in a horizontal direction in units of an interval of one-half of the transmission sampling interval or less by a one-dimensional or two-demensional spacial filter. Futhermore, the time compressed color difference signal is compensaed for in a vertical direction by a distance corresponding to the amount of a vertical motion vector. On this occasion, a time compressed color difference signal to be inserted into a position to be interpolated in the present frame is produced using a time compressed color difference signal in a position spaced apart from the position to be interpolated by a distance corresponding to the amount of the vertical motion vector such that the time compressed color difference signal to be inserted becomes the same type of color difference signal as other time compressed color difference signals on a line to which the position to be interpolated belongs.

公开(公告)号：US06363063B1

公开(公告)日：2002-03-26

申请号：US09047824

申请日：1998-03-25

申请人： Kazuhiro Kimura ,  Shigeaki Hayashibe ,  Takahiko Masumoto ,  Yutaka Hirakoso ,  Hiroshi Kaneko

发明人： Kazuhiro Kimura ,  Shigeaki Hayashibe ,  Takahiko Masumoto ,  Yutaka Hirakoso ,  Hiroshi Kaneko

IPC分类号： H04B700

CPC分类号： H03J1/0066 ,  H04H20/22 ,  H04H60/37 ,  H04H2201/13

摘要： A receiver receives FM multiplex broadcast data of both RDS and DARC systems by using one front end. A BIC detection circuit (101) detects a block identification code (BIC) included in received data. A coincidence/non-coincidence detection circuit (104) judges whether or not a BIC detection timing is correct and emits a coincidence/non-coincidence pulse. A forward protection circuit (106) counts a frequency of outputs of non-coincidence pulses and retains an established synchronous condition until the counted value exceeds a predetermined value. Then, a forward protection control circuit (108) inhibits the forward protection circuit from performing a count operation while a search is performed for selecting a station. Also, a rearward protection circuit (105) counts a frequency of outputs of coincidence pulses and establishes a synchronous condition when the counted value reaches a predetermined value. Further, a rearward protection control circuit (800) inhibits the rearward protection circuit from performing a count operation while a search is performed.

摘要翻译： 接收机通过使用一个前端接收RDS和DARC系统的FM多路复用广播数据。 BIC检测电路（101）检测包含在接收数据中的块识别码（BIC）。 一致/不符合检测电路（104）判断BIC检测定时是否正确并且发出一致/非重合脉冲。 正向保护电路（106）对不一致脉冲的输出频率进行计数，并保持建立的同步状态，直到计数值超过预定值。 然后，当进行用于选择站的搜索时，前向保护控制电路（108）禁止前向保护电路执行计数操作。 此外，后方保护电路（105）对一致脉冲的输出频率进行计数，并且当计数值达到预定值时建立同步状态。 此外，在执行搜索时，后向保护控制电路（800）禁止后向保护电路执行计数操作。

公开(公告)号：US06256359B1

公开(公告)日：2001-07-03

申请号：US08840988

申请日：1997-04-21

申请人： Takahiko Masumoto ,  Kazuhiro Kimura ,  Hiroshi Kaneko

发明人： Takahiko Masumoto ,  Kazuhiro Kimura ,  Hiroshi Kaneko

IPC分类号： H04L512

CPC分类号： H04L27/2332 ,  H04H20/22 ,  H04H60/44 ,  H04H2201/13 ,  H04L2027/0028 ,  H04L2027/0048

摘要： Received signals are digitized by a comparator, and sampled by regenerated clock signals synchronized to a carrier. Biphase symbol data are demodulated based on the sampling data. A biphase decoder circuit performs subtraction of the biphase symbol data to be paired. The subtraction result is compared with threshold values by data judgment circuitry which then judges inversion of the biphase signals to be paired. An RDS-ID detector circuit detects inversion of RDS signals by detection of either continuity or a ratio of signals received for a certain length period. Alternatively, RDS signals are detected by stability of output from the pair judgment circuit to detect a combination of biphase symbols.

摘要翻译： 接收信号由比较器数字化，并通过与载波同步的再生时钟信号采样。 基于采样数据对双相符号数据进行解调。 双相解码器电路执行要配对的双相符号数据的减法。 通过数据判断电路将减法结果与阈值进行比较，然后数据判断电路判断双相信号的配对倒置。 RDS-ID检测器电路通过检测在一定长度周期内接收的信号的连续性或比率来检测RDS信号的反转。 或者，通过对对判断电路的输出的稳定性来检测RDS信号，以检测双相符号的组合。

公开(公告)号：US5752176A

公开(公告)日：1998-05-12

申请号：US624739

申请日：1996-03-26

申请人： Kazuhiro Kimura ,  Shigeaki Hayashibe ,  Yutaka Hirakoso ,  Takahiko Masumoto ,  Shizuka Ishimura ,  Toshiyuki Ozawa ,  Munehiro Suka

发明人： Kazuhiro Kimura ,  Shigeaki Hayashibe ,  Yutaka Hirakoso ,  Takahiko Masumoto ,  Shizuka Ishimura ,  Toshiyuki Ozawa ,  Munehiro Suka

IPC分类号： H04B1/16 ,  H04B1/18

CPC分类号： H04B1/1646 ,  H04H20/26 ,  H04H20/30 ,  H04H20/22 ,  H04H2201/15

摘要： An SI judging circuit in a service detecting section detects a service identification code included in a block included in received superimposed FM data. When the block represents an unnecessary service, the SI judging circuit generates a predetermined service detecting signal, which is supplied to a station selecting microcomputer. A user operates a station selecting key to request the change of the broadcasting station. When the change is requested, and also the service detecting signal indicating that the service included in the received block is not needed is supplied to the station selecting microcomputer by the SI judging circuit, a control section of the station selecting microcomputer outputs station data corresponding to the requested station to a PLL synthesizer, and then the frequency signal (tuning frequency) is changed at a front end. This enables data received during a period for receiving blocks for unnecessary services to be NG, and can prevent data of blocks including necessary services from being NG.

摘要翻译： 服务检测部分中的SI判断电路检测包含在接收到的叠加FM数据中的块中的服务识别码。 当该块表示不必要的服务时，SI判断电路产生预定的服务检测信号，该信号被提供给站选择微计算机。 用户操作站选择键以请求改变广播电台。 当请求改变，并且指示包含在接收块中的服务不需要的服务检测信号通过SI判断电路提供给站选择微计算机时，站选择微机的控制部分输出对应于 所请求的站到PLL合成器，然后在前端改变频率信号（调谐频率）。 这使得在用于接收不必要服务的块的周期期间接收的数据为NG，并且可以防止包括必需服务的块的数据成为NG。

公开(公告)号：US5018010A

公开(公告)日：1991-05-21

申请号：US476069

申请日：1990-02-01

申请人： Takahiko Masumoto

发明人： Takahiko Masumoto

IPC分类号： H04N5/21 ,  H04N7/015 ,  H04N7/12

CPC分类号： H04N7/015 ,  H04N7/125

摘要： Disclosed is a MUSE decoder for a pixel signal sampled in accordance with Multiple Sub-nyquist Sampling Encoding (MUSE). An interframe interpolation circuit (142) applies a pixel signal Sg which is not subjected to noise reduction processing to an intrafield interpolation circuit (18') for motion picture processing through a signal line (L5). A pixel signal delayed, which is outputted from delay circuits (24a, 24b) is subjected to a required noise reduction processing by an adder 60. Since the intrafield interpolation circuit 18' receives the pixel signal Sg which is not subjected to the noise reduction processing, an adverse influence on a motion picture, which may be caused by the noise reduction, is prevented even in case that the delay circuits (24a, 24b) are shared for motion picture processing and still picture processing.

摘要翻译： 公开了一种用于根据多子尼奎斯特采样编码（MUSE）采样的像素信号的MUSE解码器。 帧间插值电路（142）通过信号线（L5）将没有进行降噪处理的像素信号Sg应用于用于运动图像处理的场内插值电路（18分钟）。 由延迟电路24a，24b输出的像素信号被延迟，由加法器60进行所需的降噪处理。由于场内插补电路18分钟接收未进行降噪处理的像素信号Sg 即使延迟电路（24a，24b）被共享用于运动图像处理和静止图像处理，也可以防止由噪声降低引起的对运动图像的不良影响。

公开(公告)号：US07110557B2

公开(公告)日：2006-09-19

申请号：US09818249

申请日：2001-03-26

申请人： Yoshihiko Kon ,  Takashi Uchino ,  Hiroshi Kaneko ,  Takahiko Masumoto

发明人： Yoshihiko Kon ,  Takashi Uchino ,  Hiroshi Kaneko ,  Takahiko Masumoto

IPC分类号： H03G3/00

CPC分类号： H03G3/3089 ,  H03G3/001

摘要： Volume adjustment is performed in small steps at a DSP (12) and volume adjustment is performed in wide steps at electronic volume circuits (18L, 18R). Adjustment only by the DSP (12) is performed for a small volume range less than or equal to a predetermined level. For a volume higher than or equal to the predetermined level, fine adjustment by the DSP (12) at the transient period of volume adjustment is combined to reduce the increment of variation so that the volume adjustment is performed gradually.

摘要翻译： 在DSP（12）处以小步骤进行音量调节，并且在电子体积电路（18L，18R）上以宽的步长进行音量调节。 对于小于或等于预定电平的小体积范围，仅对DSP（12）进行调整。 对于高于或等于预定电平的音量，组合音量调节过程中DSP（12）的微调，以减小变化的增量，从而逐渐进行音量调节。

公开(公告)号：US5809094A

公开(公告)日：1998-09-15

申请号：US654858

申请日：1996-05-29

申请人： Takahiko Masumoto ,  Kazuhiro Kimura ,  Hiroshi Kaneko

发明人： Takahiko Masumoto ,  Kazuhiro Kimura ,  Hiroshi Kaneko

IPC分类号： H04H40/18 ,  H04J3/06 ,  H04L7/00

CPC分类号： H04J3/0608 ,  H04H40/18 ,  H04H2201/13

摘要： An offset circuit (2) detects an offset word serving as a synchronization pattern. By being triggered by the detection, main and subordinate synchronization detection circuits (5 and 6) detect the periodicity of the offset word only during a predetermined backward guard period. Both synchronization detection circuits (5 and 6) detect offset words at different timings. Therefore, if one synchronization detection circuit (5 or 6) fails in detection of synchronization, it is possible to use a detection result of the other synchronization detection circuit (5 or 6). Moreover, received data during the backward guard period is stored in a data memory (11). Therefore, it is possible to use the stored data as received data after detection of synchronization. Even after establishment of synchronization, the synchronization detection circuit (5 or 6) continuously detects the periodicity of an offset word at a timing different from an established timing. Therefore, when established synchronization is incorrect, it can immediately be corrected.

摘要翻译： 偏移电路（2）检测作为同步模式的偏移字。 通过检测触发，主要和从属同步检测电路（5和6）仅在预定的后退保护周期期间检测偏移字的周期。 两个同步检测电路（5和6）在不同的定时检测偏移字。 因此，如果一个同步检测电路（5或6）在同步检测中失败，则可以使用另一个同步检测电路（5或6）的检测结果。 此外，在后向保护期间的接收数据存储在数据存储器（11）中。 因此，可以在检测到同步之后将所存储的数据用作接收数据。 即使在同步建立之后，同步检测电路（5或6）在与建立的定时不同的定时连续检测偏移字的周期。 因此，当建立同步不正确时，可以立即进行更正。