-
1.发明授权FM multiplex broadcast receiving circuit for detecting presence or absence of multiplex information 失效FM多路复用广播接收电路，用于检测多路复用信息的存在或不存在
公开(公告)号：US5802067A
公开(公告)日：1998-09-01
申请号：US614466
申请日：1996-03-12
申请人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
发明人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
CPC分类号： H04H20/34 , H04H40/18 , H04H2201/13
摘要： In accordance with the operation of an operating section 14, a control section 12 performs a reception control operation and demodulates a signal passing through a band pass filter 7 for extracting a multiplex signal using a multiplex signal demodulating section 8 when receiving a broadcast signal. A block synchronization circuit 16 of a synchronization circuit 9 carries out block synchronization processing on the demodulated signal. When block synchronization is established, a synchronization determination signal is supplied to a detecting section DET and the detecting section DET determines that a broadcasting station whose radio waves are currently being received is a multiplex broadcasting station.
摘要翻译： 根据操作部分14的操作，控制部分12在接收广播信号时，执行接收控制操作并且解调通过带通滤波器7的信号，以使用多路复用信号解调部分8提取多路复用信号。 同步电路9的块同步电路16对解调信号执行块同步处理。 当建立块同步时，将同步确定信号提供给检测部分DET，并且检测部分DET确定当前正在接收无线电波的广播电台是多路复用广播电台。
-
2.发明授权Digital signal processing for controlling error correction based on the state of the control bit 失效数字信号处理，用于根据控制位的状态控制纠错
公开(公告)号：US5757825A
公开(公告)日：1998-05-26
申请号：US588639
申请日：1996-01-19
申请人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
发明人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
CPC分类号： H04L1/0065 , H04L1/0057 , H04L1/0061
摘要： In multiplex FM broadcasting, a digital signal is composed of a frame which consists of a predetermined number of blocks in the vertical direction, a block consisting of a predetermined number of bits in the horizontal direction and having a horizontal parity (error correcting code) for correcting errors in the horizontal direction and a vertical parity for correcting errors in the vertical direction. The block also has a control bit for determining whether the error correction in the horizontal direction is to be carried out only once. A decoding identification detector (20) detects the content of the control bit, a controller (12) controls the re-writing of the digital signal into a frame buffer (13) after the error correction of the digital signal in the vertical direction by an error corrector (14). The controller (12) also controls the provision of the digital signal stored in the buffer (13) to the error corrector (14) according to the content of the control bit, determining whether the second error correction in the horizontal direction is to be carried out.
摘要翻译： 在多路复用FM广播中，数字信号由在垂直方向上由预定数量的块组成的帧构成，由水平方向上的预定数量的比特组成的块，并且具有水平奇偶校验码（纠错码） 校正水平方向上的误差和用于校正垂直方向上的误差的垂直奇偶校验。 该块还具有用于确定水平方向上的纠错是否仅被执行一次的控制位。 解码识别检测器（20）检测控制位的内容，控制器（12）在垂直方向的数字信号的纠错之后控制数字信号重新写入帧缓冲器（13） 误差校正器（14）。 控制器（12）还根据控制位的内容控制向缓冲器（13）中存储的数字信号的提供给纠错器（14），确定是否要携带水平方向上的第二纠错 出来
-
公开(公告)号：US5960328A
公开(公告)日：1999-09-28
申请号：US622048
申请日：1996-03-26
申请人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
发明人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
IPC分类号： H04B1/16
CPC分类号： H04H20/26 , H04B1/1646 , H04H20/34 , H04H20/22 , H04H2201/15
摘要： Superimposed FM data is demodulated to digital data. A synchronism reproducing circuit (data block detecting section) detects the front of blocks in the digital data to generate a block head signal (a station change timing signal), which is supplied to a control section of a station selecting microcomputer. When a station selecting key requests a change of the received station, station data corresponding to a requested station is supplied to the control section (a station selecting control section). When the block head signal is inputted after requesting the change of the station, the control section begins to output station change data to a PLL frequency synthesizer in order to change the frequency signal in a front end. This prevents a latter part of a block in received superimposed FM data from being NG data.
摘要翻译： 叠加的FM数据被解调为数字数据。 同步再现电路（数据块检测部分）检测数字数据中的块的前端以产生提供给站选择微计算机的控制部分的块头信号（站改变定时信号）。 当站选择键请求改变接收站时，与所请求站对应的站数据被提供给控制区（站选择控制区）。 当在请求改变站之后输入块头信号时，控制部分开始向PLL频率合成器输出站改变数据，以改变前端的频率信号。 这防止接收到的叠加的FM数据中的块的后半部分成为NG数据。
-
公开(公告)号：US5752176A
公开(公告)日：1998-05-12
申请号：US624739
申请日：1996-03-26
申请人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
发明人： Kazuhiro Kimura , Shigeaki Hayashibe , Yutaka Hirakoso , Takahiko Masumoto , Shizuka Ishimura , Toshiyuki Ozawa , Munehiro Suka
CPC分类号： H04B1/1646 , H04H20/26 , H04H20/30 , H04H20/22 , H04H2201/15
摘要： An SI judging circuit in a service detecting section detects a service identification code included in a block included in received superimposed FM data. When the block represents an unnecessary service, the SI judging circuit generates a predetermined service detecting signal, which is supplied to a station selecting microcomputer. A user operates a station selecting key to request the change of the broadcasting station. When the change is requested, and also the service detecting signal indicating that the service included in the received block is not needed is supplied to the station selecting microcomputer by the SI judging circuit, a control section of the station selecting microcomputer outputs station data corresponding to the requested station to a PLL synthesizer, and then the frequency signal (tuning frequency) is changed at a front end. This enables data received during a period for receiving blocks for unnecessary services to be NG, and can prevent data of blocks including necessary services from being NG.
摘要翻译： 服务检测部分中的SI判断电路检测包含在接收到的叠加FM数据中的块中的服务识别码。 当该块表示不必要的服务时，SI判断电路产生预定的服务检测信号，该信号被提供给站选择微计算机。 用户操作站选择键以请求改变广播电台。 当请求改变，并且指示包含在接收块中的服务不需要的服务检测信号通过SI判断电路提供给站选择微计算机时，站选择微机的控制部分输出对应于 所请求的站到PLL合成器，然后在前端改变频率信号（调谐频率）。 这使得在用于接收不必要服务的块的周期期间接收的数据为NG，并且可以防止包括必需服务的块的数据成为NG。
-
公开(公告)号：US06363063B1
公开(公告)日：2002-03-26
申请号：US09047824
申请日：1998-03-25
IPC分类号： H04B700
CPC分类号： H03J1/0066 , H04H20/22 , H04H60/37 , H04H2201/13
摘要： A receiver receives FM multiplex broadcast data of both RDS and DARC systems by using one front end. A BIC detection circuit (101) detects a block identification code (BIC) included in received data. A coincidence/non-coincidence detection circuit (104) judges whether or not a BIC detection timing is correct and emits a coincidence/non-coincidence pulse. A forward protection circuit (106) counts a frequency of outputs of non-coincidence pulses and retains an established synchronous condition until the counted value exceeds a predetermined value. Then, a forward protection control circuit (108) inhibits the forward protection circuit from performing a count operation while a search is performed for selecting a station. Also, a rearward protection circuit (105) counts a frequency of outputs of coincidence pulses and establishes a synchronous condition when the counted value reaches a predetermined value. Further, a rearward protection control circuit (800) inhibits the rearward protection circuit from performing a count operation while a search is performed.
摘要翻译： 接收机通过使用一个前端接收RDS和DARC系统的FM多路复用广播数据。 BIC检测电路（101）检测包含在接收数据中的块识别码（BIC）。 一致/不符合检测电路（104）判断BIC检测定时是否正确并且发出一致/非重合脉冲。 正向保护电路（106）对不一致脉冲的输出频率进行计数，并保持建立的同步状态，直到计数值超过预定值。 然后，当进行用于选择站的搜索时，前向保护控制电路（108）禁止前向保护电路执行计数操作。 此外，后方保护电路（105）对一致脉冲的输出频率进行计数，并且当计数值达到预定值时建立同步状态。 此外，在执行搜索时，后向保护控制电路（800）禁止后向保护电路执行计数操作。
-
公开(公告)号：US06118831A
公开(公告)日：2000-09-12
申请号：US840970
申请日：1997-04-21
CPC分类号： H04L27/2332 , H04H40/18 , H04H2201/13 , H04L2027/0046
摘要： An RDS signal is binarized by a comparator (2) and the output is sampled by a regeneration clock in synchronism with a regeneration carrier to provide sampled data. Then, by means of an accumulator (an adder 6 and a D-FF7) or a low pass filter (12), an integration result of the sampled output is obtained for each biphase symbol and by means of a biphase decoder circuit (9), the integration results are subjected to a subtraction between two symbols making up a pair. A differentially coded RDS data can be obtained using the sign of the subtraction result, which is differentially decoded in a differential decoder circuit (11) to provide an RDS data. In addition, the absolute value of the subtraction result is compared with a predetermined threshold value to provide reliability data for each differentially coded RDS data using the comparison result. The lower one of the consecutive reliability data may be assumed to be the reliability data for the RDS data.
摘要翻译： RDS信号由比较器（2）二值化，并且通过与再生载体同步的再生时钟对输出进行采样，以提供采样数据。 然后，通过累加器（加法器6和D-FF7）或低通滤波器（12），对于每个双相符号获得采样输出的积分结果，并通过双相解码器电路（9）获得积分结果， ，整合结果在构成一对的两个符号之间进行减法。 可以使用在差分解码器电路（11）中进行差分解码的减法结果的符号来获得差分编码的RDS数据，以提供RDS数据。 此外，将减法结果的绝对值与预定阈值进行比较，以使用比较结果为每个差分编码的RDS数据提供可靠性数据。 可以将连续可靠性数据中的较低的一个假定为RDS数据的可靠性数据。
-
公开(公告)号：US5809094A
公开(公告)日：1998-09-15
申请号：US654858
申请日：1996-05-29
CPC分类号： H04J3/0608 , H04H40/18 , H04H2201/13
摘要： An offset circuit (2) detects an offset word serving as a synchronization pattern. By being triggered by the detection, main and subordinate synchronization detection circuits (5 and 6) detect the periodicity of the offset word only during a predetermined backward guard period. Both synchronization detection circuits (5 and 6) detect offset words at different timings. Therefore, if one synchronization detection circuit (5 or 6) fails in detection of synchronization, it is possible to use a detection result of the other synchronization detection circuit (5 or 6). Moreover, received data during the backward guard period is stored in a data memory (11). Therefore, it is possible to use the stored data as received data after detection of synchronization. Even after establishment of synchronization, the synchronization detection circuit (5 or 6) continuously detects the periodicity of an offset word at a timing different from an established timing. Therefore, when established synchronization is incorrect, it can immediately be corrected.
摘要翻译： 偏移电路（2）检测作为同步模式的偏移字。 通过检测触发，主要和从属同步检测电路（5和6）仅在预定的后退保护周期期间检测偏移字的周期。 两个同步检测电路（5和6）在不同的定时检测偏移字。 因此，如果一个同步检测电路（5或6）在同步检测中失败，则可以使用另一个同步检测电路（5或6）的检测结果。 此外，在后向保护期间的接收数据存储在数据存储器（11）中。 因此，可以在检测到同步之后将所存储的数据用作接收数据。 即使在同步建立之后，同步检测电路（5或6）在与建立的定时不同的定时连续检测偏移字的周期。 因此，当建立同步不正确时，可以立即进行更正。
-
公开(公告)号：US06256359B1
公开(公告)日：2001-07-03
申请号：US08840988
申请日：1997-04-21
IPC分类号： H04L512
CPC分类号： H04L27/2332 , H04H20/22 , H04H60/44 , H04H2201/13 , H04L2027/0028 , H04L2027/0048
摘要： Received signals are digitized by a comparator, and sampled by regenerated clock signals synchronized to a carrier. Biphase symbol data are demodulated based on the sampling data. A biphase decoder circuit performs subtraction of the biphase symbol data to be paired. The subtraction result is compared with threshold values by data judgment circuitry which then judges inversion of the biphase signals to be paired. An RDS-ID detector circuit detects inversion of RDS signals by detection of either continuity or a ratio of signals received for a certain length period. Alternatively, RDS signals are detected by stability of output from the pair judgment circuit to detect a combination of biphase symbols.
摘要翻译： 接收信号由比较器数字化，并通过与载波同步的再生时钟信号采样。 基于采样数据对双相符号数据进行解调。 双相解码器电路执行要配对的双相符号数据的减法。 通过数据判断电路将减法结果与阈值进行比较，然后数据判断电路判断双相信号的配对倒置。 RDS-ID检测器电路通过检测在一定长度周期内接收的信号的连续性或比率来检测RDS信号的反转。 或者，通过对对判断电路的输出的稳定性来检测RDS信号，以检测双相符号的组合。
-
公开(公告)号：US6017146A
公开(公告)日：2000-01-25
申请号：US654859
申请日：1996-05-29
CPC分类号： H04H40/18 , H04H2201/13
摘要： A demodulating circuit demodulates a received signal, and outputs patterns of demodulated data and reliability information bits indicating correctness of the demodulated data. These are supplied to first and second shift registers (4 and 5), respectively. When the number of reliability information bits of Level 1 in the second shift register is a predetermined value or less, a shift operation is repeated a plurality of times. When a reliability information bit of Level 1 is outputted, an error correction control circuit (7) successively outputs all possible bit patterns of the demodulated data An EXOR gate (10) generates all possible patterns of demodulated data An error correcting circuit (11) carries out error correction for all the patterns. When the number is larger than the predetermined value, the error correction is carried out only for the demodulated data supplied from the demodulating circuit in a conventional manner.
摘要翻译： 解调电路对接收到的信号进行解调，并且输出解调数据的模式和指示解调数据的正确性的可靠性信息比特。 这些分别被提供给第一和第二移位寄存器（4和5）。 当第二移位寄存器中的级别1的可靠性信息位的数量是预定值或更小时，多次重复移位操作。 当输出级别1的可靠性信息位时，纠错控制电路（7）连续地输出解调数据的所有可能的位模式。EXOR门（10）产生解调数据的所有可能的模式。纠错电路（11） 出错纠正所有的模式。 当该数量大于预定值时，仅对于从解调电路以常规方式提供的解调数据进行纠错。
-
公开(公告)号：US5777511A
公开(公告)日：1998-07-07
申请号：US840477
申请日：1997-04-21
CPC分类号： H04L7/0334 , H04H40/18 , H04L7/0331 , H04H2201/13
摘要： A digital modulating signal, which is a binary conversion of an RDS signal by a comparator, is sampled by a D-FF with a regeneration clock synchronized with a carrier regenerated by a carrier regeneration circuit. Next, a comparator output is input by an edge detection circuit where a data edge is detected, and the edge interval between this edge and the sampling timing edge of the regeneration clock is detected by a reliability judgment circuit where the edge interval is encoded and output as reliability data. Then, the reliability data is added as LSB data to various sampling data, and data for various symbols is regenerated at the data regeneration circuit. This minimizes the influence of the error data on the data regeneration circuit even if data is sampled erroneously.
摘要翻译： 作为比较器的RDS信号的二进制转换的数字调制信号由具有与由载波再生电路再生的载波同步的再生时钟的D-FF进行采样。 接下来，比较器输出由边缘检测电路输入，其中检测到数据边缘，并且该边沿与再生时钟的采样定时边缘之间的边缘间隔由可靠性判断电路检测，其中边缘间隔被编码和输出 作为可靠性数据。 然后，将可靠性数据作为LSB数据添加到各种采样数据，并且在数据再生电路再生各种符号的数据。 即使数据被错误地采样，这也使误差数据对数据再生电路的影响最小化。
-
-
-
-
-
-
-
-
-
搜索结果
15 条记录 (耗时 0.028 秒)
