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公开(公告)号：US5740092A
公开(公告)日：1998-04-14
申请号：US299598
申请日：1994-09-01
CPC分类号： G06F17/15 , G06F15/78 , G06F17/10 , G06F9/3012 , G06F9/462
摘要： In order to establish connections of plural arithmetic units capable of performing basic functions such as filtering in various connection ways, a bus switch is provided which has a plurality of input data lines connected with output terminals of the arithmetic units, at least one external input data line, a plurality of output data lines connected with input terminals of the arithmetic units, and at least one external output data line. In addition, two register sets are provided which hold arithmetic control information designating contents of processes to be performed by the arithmetic units and connection control information designating connection ways within the bus switch. Depending on the broadcasting system, information held by one of the register sets and information held by the other are updated, and, according to a process algorithm, either one of the two register sets is selected. As a result of such arrangement, a single piece of image processing hardware can be shared between different broadcasting systems as well as between different algorithms.
摘要翻译： 为了建立能够执行诸如以各种连接方式进行滤波的基本功能的多个运算单元的连接，提供总线开关，其具有与运算单元的输出端连接的多个输入数据线，至少一个外部输入数据 与运算单元的输入端连接的多个输出数据线，以及至少一个外部输出数据线。 此外，提供两个寄存器组，其存储指定由运算单元执行的处理的内容的算术控制信息和指定总线开关内的连接方式的连接控制信息。 根据广播系统，更新由寄存器组中的一个和另一个保存的信息的信息，并且根据处理算法选择两个寄存器组中的任一个。 作为这种安排的结果，可以在不同的广播系统之间以及不同的算法之间共享单个图像处理硬件。
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2.发明授权Video signal processor and method for processing a scanning line regardless of the synchronizing signal 失效视频信号处理器和用于处理扫描线的方法，而不管同步信号如何
公开(公告)号：US5555197A
公开(公告)日：1996-09-10
申请号：US226663
申请日：1994-04-11
CPC分类号： H04N9/642 , H04N5/46 , H04N7/0152 , H04N5/907
摘要： A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.
摘要翻译： 协处理器被并入包括CPU，指令高速缓存，数据存储器，总线控制器，中断控制部分和DMA控制器的处理器中。 该协处理器具有并行产品总和运算部分，比较器，I / O寄存器部分和产品总和因子寄存器部分。 在输入侧提供的帧存储器存储每像素数字化的MUSE或NTSC信号。 DMA控制输入侧帧存储器和数据存储器之间的数据传送以及在输出侧提供的帧存储器与数据存储器之间的数据传送。 存储在数据存储器中的像素数据根据广播系统通过基于软件的乘积因子的切换进行处理。
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3.发明授权Signal processor capable of sharing common hardware in a plural processing system 失效能够在多个处理系统中共享公共硬件的信号处理器
公开(公告)号：US5771185A
公开(公告)日：1998-06-23
申请号：US768085
申请日：1996-12-16
CPC分类号： G06F17/15 , G06F15/78 , G06F17/10 , G06F9/3012 , G06F9/462
摘要： In order to establish connections of plural arithmetic units capable of performing basic functions such as filtering in various connection ways, a bus switch is provided which has a plurality of input data lines connected with output terminals of the arithmetic units, at least one external input data line, a plurality of output data lines connected with input terminals of the arithmetic units, and at least one external output data line. In addition, two register sets are provided which hold arithmetic control information designating contents of processes to be performed by the arithmetic units and connection control information designating connection ways within the bus switch. Depending on the broadcasting system, information held by one of the register sets and information held by the other are updated, and, according to a process algorithm, either one of the two register sets is selected. As a result of such arrangement, a single piece of image processing hardware can be shared between different broadcasting systems as well as between different algorithms.
摘要翻译： 为了建立能够执行诸如以各种连接方式进行滤波的基本功能的多个运算单元的连接，提供总线开关，其具有与运算单元的输出端连接的多个输入数据线，至少一个外部输入数据 与运算单元的输入端连接的多个输出数据线，以及至少一个外部输出数据线。 此外，提供两个寄存器组，其存储指定由运算单元执行的处理的内容的算术控制信息和指定总线开关内的连接方式的连接控制信息。 根据广播系统，更新由寄存器组中的一个和另一个保存的信息的信息，并且根据处理算法选择两个寄存器组中的任一个。 作为这种安排的结果，可以在不同的广播系统之间以及不同的算法之间共享单个图像处理硬件。
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4.发明授权Processing of pixel data at an operating frequency higher than the sampling rate of the input signal 失效以比输入信号的采样率高的工作频率处理像素数据
公开(公告)号：US5751375A
公开(公告)日：1998-05-12
申请号：US798824
申请日：1997-02-12
CPC分类号： H04N5/46 , H04N7/0152 , H04N9/642 , H04N5/907
摘要： A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.
摘要翻译： 协处理器被并入包括CPU，指令高速缓存，数据存储器，总线控制器，中断控制部分和DMA控制器的处理器中。 该协处理器具有并行产品总和运算部分，比较器，I / O寄存器部分和产品总和因子寄存器部分。 在输入侧提供的帧存储器存储每像素数字化的MUSE或NTSC信号。 DMA控制输入侧帧存储器和数据存储器之间的数据传送以及在输出侧提供的帧存储器与数据存储器之间的数据传送。 存储在数据存储器中的像素数据根据广播系统通过基于软件的乘积因子的切换进行处理。
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公开(公告)号：US5886912A
公开(公告)日：1999-03-23
申请号：US557316
申请日：1995-11-14
申请人： Jiro Miyake , Kazuki Ninomiya , Tamotsu Nishiyama
发明人： Jiro Miyake , Kazuki Ninomiya , Tamotsu Nishiyama
CPC分类号： H03H17/0283
摘要： A plurality of processing elements are connected in cascade so as to constitute a single signal processing apparatus. The signal processing apparatus has a first path for transferring an input data signal and a second path for transferring a processing result of the input data signal. Each of the processing elements has a first input disposed on the first path, a data holding circuit for holding the data signal supplied through the first input, a product-sum circuit for executing a product-sum operation between the data signal held in the data holding circuit and another data signal, a second input disposed on the second path so as to supply the other data signal to the product-sum circuit, a result register for holding the result of the operation calculated by the product-sum circuit and supplying the held result of the operation to the second path, an output selecting circuit for supplying either one of the data signal held in the data holding circuit and the result of the operation held in the result register, and a processing control circuit for controlling respective operations of the data holding circuit, product-sum circuit, result register, and output selecting circuit. Since a route extending from the result register to the output selecting circuit forms a bypass from the second path to the first path, a flexible process can be performed by the signal processing apparatus by using or not using the bypass depending on control information.
摘要翻译： 多个处理元件级联连接成构成单个信号处理装置。 信号处理装置具有用于传送输入数据信号的第一路径和用于传送输入数据信号的处理结果的第二路径。 每个处理元件具有设置在第一路径上的第一输入端，用于保持通过第一输入端提供的数据信号的数据保持电路，用于在保持在数据中的数据信号之间执行乘积和运算的乘积和电路 保持电路和另一数据信号，第二输入设置在第二路径上，以便将其他数据信号提供给乘积和电路;结果寄存器，用于保持由乘积和电路计算的运算结果，并提供 保持对第二路径的操作结果，输出选择电路，用于提供保持在数据保持电路中的数据信号中的任一个和结果寄存器中保存的操作结果;以及处理控制电路，用于控制 数据保持电路，积和电路，结果寄存器和输出选择电路。 由于从结果寄存器延伸到输出选择电路的路由形成从第二路径到第一路径的旁路，所以可以由信号处理装置根据控制信息使用或不使用旁路来执行灵活处理。
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公开(公告)号：US5777688A
公开(公告)日：1998-07-07
申请号：US644784
申请日：1996-05-10
摘要： A plurality of signal processing elements are cascade-connected to form a signal processor having three signal paths. The signal processor is a small-sized device which can be shared by sum-of-products calculation and division. In each signal processing element, first and second shifters and an adder-subtracter are used for performing shift addition for multiplication of a variable by a constant which is a basis of the sum-of-products calculation. The adder-subtracter and a third shifter for shifting a result obtained by the adder-subtracter are used for performing subtraction and shifting for obtaining a partial quotient and a partial remainder of division. The partial quotient thus obtained is transferred to the signal processing element in the next stage through a flag holding circuit.
摘要翻译： 多个信号处理元件被级联连接以形成具有三个信号路径的信号处理器。 信号处理器是一个小型设备，可以通过产品总和的计算和划分来共享。 在每个信号处理元件中，第一和第二移位器和加法器减法器用于执行用于将变量乘以作为乘积和计算的基础的常数的移位加法。 加法器 - 减法器和用于移位由加减法器获得的结果的第三移位器用于执行减法和移位以获得部分商和部分余数除法。 这样获得的部分商通过标志保持电路在下一级传送到信号处理元件。
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公开(公告)号：US5703800A
公开(公告)日：1997-12-30
申请号：US545204
申请日：1995-10-19
申请人： Kazuki Ninomiya , Keizo Sumida , Jiro Miyake , Tamotsu Nishiyama
发明人： Kazuki Ninomiya , Keizo Sumida , Jiro Miyake , Tamotsu Nishiyama
CPC分类号： G06F15/8046 , G06F15/8023
摘要： An improved signal processor is disclosed which is suitable for convergence processing of images that achieves parallel processing with a smaller bus structure. An arithmetic array is provided which is formed of ten arithmetic cells capable of concurrently operating. Each arithmetic cell is specified by a denotation of E�(column number),y(row number)! where the column number x is 1.ltoreq.x.ltoreq.4 and the row number y is x.ltoreq.y.ltoreq.4. Each arithmetic cell has a multiplier and an adder for multiply-add operation. An arithmetic cell, specified by E�x,y! where 2.ltoreq.x.ltoreq.4 and x.ltoreq.y.ltoreq.4, receives data from an E�x-1,y! arithmetic cell via a direct bus as well as from an E�x-1,y-1! arithmetic cell via an oblique bus. For example, when pixel data items as to four pixels horizontally arranged in an image are fed to the four arithmetic cells in the first column, the arithmetic cell in the fourth column provides a 4-tap horizontal filter operation result.
摘要翻译： 公开了一种改进的信号处理器，其适用于以较小的总线结构实现并行处理的图像的收敛处理。 提供由能够同时操作的十个算术单元形成的运算阵列。 每个算术单元由列号x为1 的E [（列号），y（行号）]的表示来指定， = 4。 每个算术单元具有用于乘法运算的乘法器和加法器。 由E [x，y]指定的算术单元，其中2
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公开(公告)号：US5572453A
公开(公告)日：1996-11-05
申请号：US387241
申请日：1995-02-13
申请人： Jiro Miyake , Kazuki Ninomiya , Tamotsu Nishiyama
发明人： Jiro Miyake , Kazuki Ninomiya , Tamotsu Nishiyama
CPC分类号： G06F15/8053 , G06F17/10 , G06F9/3867
摘要： This invention discloses an improved signal processor comprising first to third arithmetic units forming a pipeline structure, first to third control information hold circuits each of which holds control information for its corresponding arithmetic unit, first to third selection circuits, and first to third signal transfer circuits. Transfer of a selection signal is delayed by a proportional interval of time to the processing time of each arithmetic unit. In order to perform the switching of arithmetical operations in each arithmetic unit according to the data flow in the pipeline processing, each selection circuit selects among the control information hold circuits depending on the selection signal transferred and provides control information held in a selected control information hold circuit to a corresponding arithmetic unit.
摘要翻译： 本发明公开了一种改进的信号处理器，包括形成流水线结构的第一至第三算术单元，第一至第三控制信息保持电路，每个控制信息保持电路保持其对应的运算单元，第一至第三选择电路和第一至第三信号传输电路的控制信息 。 选择信号的传送比例间隔延迟到每个运算单元的处理时间。 为了根据流水线处理中的数据流执行每个算术单元中的算术运算的切换，每个选择电路根据所传送的选择信号在控制信息保持电路中进行选择，并提供保持在选择的控制信息保持中的控制信息 电路到相应的运算单元。
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9.发明授权Development supporting method and device for signal processing system and signal processing device and method 失效信号处理系统和信号处理装置及方法的开发支持方法和装置
公开(公告)号：US5926229A
公开(公告)日：1999-07-20
申请号：US544070
申请日：1995-10-17
CPC分类号： H04N5/46
摘要： According to the signal processing method of the invention, control data is previously generated by using the name of a control signal included in an object signal, and then, the object signal including the control signal is input. The name of the control signal in the control data is substituted with the content of the control signal included in the object signal, and then the object signal is processed by a signal processing unit by using the control data including the content of the control signal. Therefore, the signal processing unit can change the processing to be performed on the object signal in accordance with the content of the control signal included in the object signal.
摘要翻译： 根据本发明的信号处理方法，通过使用对象信号中包含的控制信号的名称，预先生成控制数据，然后输入包含控制信号的目标信号。 控制数据中的控制信号的名称被包含在对象信号中的控制信号的内容所代替，然后通过使用包括控制信号的内容的控制数据由信号处理单元处理对象信号。 因此，信号处理单元可以根据对象信号中包含的控制信号的内容来改变对对象信号执行的处理。
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公开(公告)号：US5751374A
公开(公告)日：1998-05-12
申请号：US618610
申请日：1996-03-20
CPC分类号： H04N5/46 , H04N7/0152 , H04N9/642 , H04N5/907
摘要： A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.
摘要翻译： 协处理器被并入包括CPU，指令高速缓存，数据存储器，总线控制器，中断控制部分和DMA控制器的处理器中。 该协处理器具有并行产品总和运算部分，比较器，I / O寄存器部分和产品总和因子寄存器部分。 在输入侧提供的帧存储器存储每像素数字化的MUSE或NTSC信号。 DMA控制输入侧帧存储器和数据存储器之间的数据传送以及在输出侧提供的帧存储器与数据存储器之间的数据传送。 存储在数据存储器中的像素数据根据广播系统通过基于软件的乘积因子的切换进行处理。
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