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公开(公告)号：US6134375A
公开(公告)日：2000-10-17
申请号：US32219
申请日：1998-02-27
CPC分类号： H04N9/8047 , H04N5/772 , H04N9/806
摘要： A first digital processor (13) generates luminance data Y and color difference data U, V, using image data D1. The processor (13) further generates separated luminance data Y1, Y2 by halving the luminance data Y, and generates a compound color difference data C by combining the color difference data U, V for output. An JPEG encoder 13 compresses the separated luminance data Y1, Y2 and the compound color difference data C to generate compressed luminance data y1, y2 and compressed color difference data c. A modulator 15 modulates the compressed luminance data y1, y2 and the compressed color difference data c to generate luminance modulated signals m1, m2 and color difference modulated signal mc. A recording/reproducing section 16 records the luminance modulated signals m1, m2 and the color difference modulated signal mc in parallel onto the first to third recording tracks of a magnetic tape (20).
摘要翻译： 第一数字处理器（13）使用图像数据D1生成亮度数据Y和色差数据U，V。 处理器（13）还通过将亮度数据Y减半来产生分离的亮度数据Y1，Y2，并通过组合色差数据U，V来输出来产生复合色差数据C. JPEG编码器13压缩分离的亮度数据Y1，Y2和复合色差数据C以产生压缩亮度数据y1，y2和压缩色差数据c。 调制器15调制压缩亮度数据y1，y2和压缩色差数据c，以产生亮度调制信号m1，m2和色差调制信号mc。 记录/再现部分16将亮度调制信号m1，m2和色差调制信号mc并行记录在磁带（20）的第一至第三记录磁道上。
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公开(公告)号：US4853782A
公开(公告)日：1989-08-01
申请号：US165691
申请日：1988-03-09
申请人： Yoshikazu Asano , Kazuo Naganawa
发明人： Yoshikazu Asano , Kazuo Naganawa
摘要： A frame synchronizing signal detecting circuit detects a frame synchronizing signal in a video signal. When the frame synchronizing signal is not detected by the frame synchronizing signal detecting circuit, a clamp level switching circuit is responsive to a switching signal from a timer circuit for generating alternately an upper clamp potential V.sub.+ and a lower clamp potential V.sub.-. When the frame synchronizing signal is detected by the frame synchronizing signal detecting circuit, the clamp level switching circuit generates a normal clamp potential V.sub.0. A clamping pulse generating circuit is responsive to an output from the frame synchronizing signal detecting circuit for generating a clamping pulse. A clamping circuit is responsive to the clamping pulse for clamping an analogue video signal at the clamp potentials V.sub.0, V.sub.+ or V.sub.- from the clamp level switching circuit.
摘要翻译： 帧同步信号检测电路检测视频信号中的帧同步信号。 当帧同步信号检测电路未检测到帧同步信号时，钳位电平切换电路响应来自定时器电路的切换信号，交替产生上钳位电位V +和下钳位电位V-。 当帧同步信号检测电路检测到帧同步信号时，钳位电平切换电路产生正常钳位电位V0。 钳位脉冲发生电路响应来自帧同步信号检测电路的输出，用于产生钳位脉冲。 钳位电路响应于钳位脉冲，用于钳位来自钳位电平开关电路的钳位电位V0，V +或V-上的模拟视频信号。
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3.发明授权Broadcast/non-broadcast MUSE signal sound decoder with a variable protection period 失效具有可变保护期的广播/非广播MUSE信号声音解码器
公开(公告)号：US5276714A
公开(公告)日：1994-01-04
申请号：US823162
申请日：1992-01-21
摘要： A MUSE sound decoder detects a broadcasting/non-broadcasting identification flag included in the control signals in an applied MUSE signal to determine whether the MUSE signal is broadcasted or non-broadcasted. The MUSE sound decoder further includes a frame synchronization protection circuit for protecting frame synchronization over a predetermined frame synchronization protection time period when the frame synchronization pattern is not detected at the proper timing. The frame synchronization protection circuit sets the frame synchronization protection time period to a long time period when the MUSE signal is determined to be a broadcasted MUSE signal, and to a short time period when the MUSE signal is determined to be a non-broadcasted MUSE signal. Appropriate muting of a sound signal can be carried out according to the condition of the received MUSE signal.
摘要翻译： MUSE声音解码器在应用的MUSE信号中检测包含在控制信号中的广播/非广播识别标志，以确定MUSE信号是广播还是不被广播。 MUSE声音解码器还包括帧同步保护电路，用于当在适当的定时未检测到帧同步模式时，在预定的帧同步保护时间段内保护帧同步。 帧同步保护电路将帧同步保护时间段设定为当MUSE信号被确定为广播的MUSE信号的长时间段时，并且将MUSE信号确定为非广播的MUSE信号的短时间段 。 可以根据接收到的MUSE信号的条件对声音信号进行合适的静音。
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