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1.发明授权Method and apparatus for controlling tint in a digital color display system 有权用于控制数字彩色显示系统中色调的方法和装置公开(公告)号：US06614488B1
公开(公告)日：2003-09-02
申请号：US09629266
申请日：2000-07-31
申请人： Kazushi Yamauchi , Masayuki Sohda
发明人： Kazushi Yamauchi , Masayuki Sohda
IPC分类号： H04N964
摘要： A method and apparatus for controlling tint in a digital color display system capable of efficiently performing tint control of displayed colors. The tint control method is executed according to the following: (1) when the maximum and the minimum among R, G, B are the maximum gray scale value and the minimum gray scale value respectively, a step of transforming the input color into a color of a different tint based on a use defined maximum transformation value and a transformation direction; (2) when the maximum and the minimum among R, G, B are Dmax and Dmin respectively, a step of transforming the input color into a color of a different tint based on a smaller transformation value and the same transformation direction; and (3) when all values R, G, B are equal, a step of not transforming the input color in accordance with any input set value.
摘要翻译： 一种用于控制能够有效地执行所显示颜色的色调控制的数字彩色显示系统中的色调的方法和装置。 色调控制方法按以下方式执行：（1）当R，G，B中的最大值和最小值分别为最大灰度值和最小灰度值时，将输入颜色变换为颜色的步骤 基于使用定义的最大变换值和变换方向的不同色调; （2）当R，G，B中的最大和最小分别为Dmax和Dmin时，基于较小的变换值和相同的变换方向将输入颜色变换成不同色调的颜色的步骤; 和（3）当所有值R，G，B都相等时，根据任何输入设定值不转换输入颜色的步骤。
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2.发明授权Color image processing method, color image processing apparatus, and liquid-crystal display 有权彩色图像处理方法，彩色图像处理装置和液晶显示器公开(公告)号：US06809714B1
公开(公告)日：2004-10-26
申请号：US09634317
申请日：2000-08-08
申请人： Kazushi Yamauchi , Masayuki Sohda
发明人： Kazushi Yamauchi , Masayuki Sohda
IPC分类号： G09G336
摘要： The present invention embodies high-accuracy white point adjustment with a simple circuit configuration according to an efficient algorithm in a display system for full digital processing. More particularly, the present invention is directed to a digital video interface 13 for inputting a digital video signal outputted from a host system and a liquid-crystal display monitor 11 for applying color conversion to the digital video signal inputted by the digital video interface 13 without using a look-up table, in which an adjusted-value input logic for inputting adjusted values at predetermined points to achromatic colors between maximum- and minimum-gray-scale achromatic colors and a controller LSI 22 for computing a digital video signal inputted by the digital video interface 13 so as to converge chromaticity coordinates for achromatic colors and outputting a computed digital value in a pipeline manner are used.
摘要翻译： 根据用于全数字处理的显示系统中的有效算法，本发明体现了具有简单电路配置的高精度白点调整。 更具体地，本发明涉及用于输入从主机系统输出的数字视频信号的数字视频接口13和用于将颜色转换应用于由数字视频接口13输入的数字视频信号的液晶显示监视器11，而没有 使用查找表，其中用于将预定点处的调整值输入到最大和最小灰度无彩色之间的无彩色的调整值输入逻辑和用于计算由第一和第二灰阶无色彩输入的数字视频信号的控制器LSI 22 数字视频接口13，以便会聚用于无彩色的色度坐标，并以管道方式输出计算的数字值。
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公开(公告)号：US5790200A
公开(公告)日：1998-08-04
申请号：US535606
申请日：1995-09-28
摘要： An arrangement for stabilizing a horizontal synchronization signal, serving as an input signal for a phase-locked loop (PLL) for generating a clock signal, by separating the horizontal synchronization signal from a composite synchronization signal including both horizontal and vertical synchronization signals. A horizontal synchronization gate signal is generated for outputting a pulse signal approximately in phase with the horizontal synchronization signal and having at least the pulse width of the horizontal synchronization signal in accordance with the composite synchronization signal and a clock pulse signal having a predetermined frequency. The horizontal synchronization signal is retrieved from the composite synchronization signal in accordance with a logical product when matching the polarity of the horizontal synchronization gate signal with the polarity of the composite synchronization signal.
摘要翻译： 通过从包括水平和垂直同步信号的复合同步信号分离水平同步信号，用于稳定水平同步信号的装置，用作用于产生时钟信号的锁相环（PLL）的输入信号。 产生水平同步门信号，用于输出与水平同步信号大致同相的脉冲信号，并且根据复合同步信号和具有预定频率的时钟脉冲信号至少具有水平同步信号的脉冲宽度。 当将水平同步门信号的极性与复合同步信号的极性相匹配时，根据逻辑积从复合同步信号中检索水平同步信号。
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公开(公告)号：US5805150A
公开(公告)日：1998-09-08
申请号：US532125
申请日：1995-09-22
CPC分类号： G09G3/3611 , G09G3/20 , H04N5/08 , H04N5/68
摘要： A synchronous signal separation circuit is disclosed which separates and fetches a synchronous signal from a video signal to which the synchronous signal has been added. The synchronous signal separation circuit includes an amplifier for amplifying a voltage of the video signal to output an amplified signal having an amplified voltage which is within a predetermined dynamic range. A voltage generator outputs a variable offset voltage to the amplifier for shifting a reference level of the amplified voltage to a predetermined level. A synchronous signal fetch means which, by comparing the amplified video signal with a threshold voltage in which the variable offset voltage has been adjusted based on the degree of amplification of the amplifier, fetches only the synchronous signal from the video signal.
摘要翻译： 公开了一种同步信号分离电路，其分离并从已经添加了同步信号的视频信号中取出同步信号。 同步信号分离电路包括放大器，用于放大视频信号的电压，以输出具有在预定动态范围内的放大电压的放大信号。 电压发生器向放大器输出可变偏移电压，以将放大电压的参考电平移动到预定电平。 同步信号提取装置，通过将放大的视频信号与基于放大器的放大程度已经调整了可变偏移电压的阈值电压进行比较，仅从视频信号中取出同步信号。
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公开(公告)号：US5272471A
公开(公告)日：1993-12-21
申请号：US957562
申请日：1992-10-07
申请人： Shigeki Asada , Masayuki Sohda , Hiroaki Yasuda
发明人： Shigeki Asada , Masayuki Sohda , Hiroaki Yasuda
CPC分类号： G06F3/1475 , G09G3/3611 , G09G2340/0414 , G09G2340/0421 , G09G2340/0442 , G09G3/2051
摘要： A display system for converting N bit signals, each representing 2.sup.N gray levels, to M bit signals representing 2.sup.M gray levels, where N is an integer larger than or equal to 2 and M is an integer satisfying N>M.gtoreq.1. Each of the N bit signals are separated into higher M bits and lower N-M bits. There are 2.sup.N-M tables, each of which stores a distinctive set of P.times.Q modification values satisfying P.times.Q.gtoreq.2.sup.N-M. One of the tables is selected using the N-M bits. Unequality between a first set of modification values and a second set of modification values of the selected table are detected. The first set of modification values and the second set of modification values are exchanged to generate a modified table of the selected table. The M bits of one N bit signal and each of the modification values of the selected table are added to generate a first set of P.times.Q M bit signals. The M bits of the next N bit signal and each of the modification values of the modified table are added to generate a second set of P.times.Q M bit signals. The first and second sets of M bit signals are provided to a display device of 2.sup.M gray levels.
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