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1.发明授权Signal transfer timing control using stored data relating to operating speeds of memory and processor 失效使用与存储器和处理器的操作速度相关的存储数据的信号传输定时控制
公开(公告)号：US4499536A
公开(公告)日：1985-02-12
申请号：US329048
申请日：1981-12-09
CPC分类号： G06F13/4243 , G06F13/38
摘要： A memory controlling apparatus retains time information prepared based on performance of a memory and a processor, and determines timing of signal exchange between the memory and the processor based on the time information. An access time to the memory is reduced while maintaining a flexibility to a change of the access time due to increase of memory capacity or reconfiguration of the memory.
摘要翻译： 存储器控制装置保持基于存储器和处理器的性能准备的时间信息，并且基于时间信息确定存储器和处理器之间的信号交换的定时。 存储器的访问时间减少，同时由于存储器容量的增加或存储器的重新配置而保持对访问时间的改变的灵活性。
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公开(公告)号：US4562491A
公开(公告)日：1985-12-31
申请号：US475407
申请日：1983-03-15
CPC分类号： G11B20/1423 , G11B20/10 , G11B5/09
摘要： A multichannel digital magnetic recording apparatus comprises a plurality (N) of modulating circuits (41 to 4N) and timing circuits (51 to 5N). Digital signals (Z1 to ZN) undergo modulation in the modulating circuits in accordance with a modulation system of a detection window Tw. The modulated signals (A1 to AN) are converted into pulse current trains by the timing circuits and then delayed such that the respective pulse currents do not occur simultaneously. Accordingly, a power capacity required of a voltage source for writing the signals by means of thin film magnetic heads (71 to 7N) is considerably decreased.
摘要翻译： 多通道数字磁记录装置包括多个（N）个调制电路（41〜4N）和定时电路（51〜5N）。 数字信号（Z1至ZN）根据检测窗口Tw的调制系统在调制电路中进行调制。 调制信号（A1至AN）由定时电路转换成脉冲电流列，然后被延迟使得各个脉冲电流不同时发生。 因此，通过薄膜磁头（71〜7N）写入信号的电压源所需的功率容量大大降低。
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