公开(公告)号：US07007262B2

公开(公告)日：2006-02-28

申请号：US10291790

申请日：2002-11-12

申请人： Keiichi Kurokawa ,  Osamu Ogawa

发明人： Keiichi Kurokawa ,  Osamu Ogawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A behavioral description is converted to a CDFG. The CDFG is scheduled in such a way that the number of registers is minimized with a desired number of clock cycles. Hardware is allocated to the scheduled results. The minimum clock period (semi-synchronous minimum clock period) attainable by adjusting clock timings for allocated registers is determined. When the semi-synchronous minimum clock period is greater than a desired clock period, all the clock timings are reset to a same value and then the positions of the registers in the CDFG are so changed as to reduce the clock period. The processing returns to the step of determining the semi-synchronous minimum clock period when the performance is improved as a result of performing retiming, or otherwise is terminated.

公开(公告)号：US06925628B2

公开(公告)日：2005-08-02

申请号：US10690957

申请日：2003-10-21

申请人： Osamu Ogawa ,  Dai Hattori ,  Keiichi Kurokawa

发明人： Osamu Ogawa ,  Dai Hattori ,  Keiichi Kurokawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A high-level synthesis method of the present invention includes: generating a CDFG (Control Data Flow Graph) based an input file describing a behavior of a digital circuit; allocating each node of the CDFG generated in the CDFG generation, expressing contents of processing, to a time synchronized with a clock called a Step, based on the CDFG and a constraint condition of the digital circuit described in a constraint file, thereby scheduling the CDFG; generating allocation information representing how resources for constituting the digital circuit are allocated to respective nodes of the CDFG scheduled in the scheduling, based on resource-level layout information representing a layout of the resources, and circuit information representing a connecting relationship between the resources; and outputting the circuit information generated in the allocation and circuit information generation.

摘要翻译： 本发明的高级合成方法包括：基于描述数字电路的行为的输入文件生成CDFG（控制数据流图）; 基于CDFG和约束文件中描述的数字电路的约束条件，将表示处理内容的CDFG生成中生成的CDFG的每个节点分配到与称为步骤的时钟同步的时间，从而调度CDFG ; 基于表示资源布局的资源级布局信息，以及表示资源之间的连接关系的电路信息，生成表示如何将用于构成数字电路的资源分配给调度调度的CDFG的各个节点的分配信息; 并输出在分配和电路信息生成中产生的电路信息。

公开(公告)号：US20050289499A1

公开(公告)日：2005-12-29

申请号：US11159291

申请日：2005-06-23

申请人： Osamu Ogawa ,  Dai Hattori ,  Keiichi Kurokawa ,  Masahiko Toyonaga

发明人： Osamu Ogawa ,  Dai Hattori ,  Keiichi Kurokawa ,  Masahiko Toyonaga

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A CDFG which is a graph representing calculations and a data flow included in the design specifications of a circuit is generated S101, a clock cycle required for the processing is obtained and thus an allocated resource connection graph is generated S102. When the allocated resource connection graph includes nodes to which hardware resources having the same function are allocated, a sharing edge for controlling sharing of the nodes is added between the nodes S103. A provisional layout of the allocated resource connection graph having the sharing edge added thereto is provided S104, and the nodes of the allocated resource connection graph are shared based on the layout result S105. The sharing edge is provided with attribute or weight such as attraction or repulsion. Thus, the distance between the nodes in the layout result is controlled and the degree at which the resources are shared is controlled.

摘要翻译： 产生表示电路设计规范中的计算和数据流的曲线图CD1G，获得处理所需的时钟周期，从而生成分配的资源连接图。当分配的资源 连接图包括分配了具有相同功能的硬件资源的节点，在节点S103之间添加用于控制节点共享的共享边。提供具有添加了共享边的已分配资源连接图的临时布局S 104，并且基于布局结果S 105共享所分配的资源连接图的节点。共享边缘被赋予诸如吸引力或排斥性的属性或权重。 因此，控制布局结果中的节点之间的距离，并且控制资源共享的程度。

公开(公告)号：US07194724B2

公开(公告)日：2007-03-20

申请号：US10991052

申请日：2004-11-16

申请人： Dai Hattori ,  Osamu Ogawa ,  Keiichi Kurokawa

发明人： Dai Hattori ,  Osamu Ogawa ,  Keiichi Kurokawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： First of all, the number of referencing of a variable described in a behavior level circuit is calculated. Next, a bit width of the variable is extracted, and a plurality of memories capable of data transferring of the extracted bit width are selected. Next, a sum of a frequency of memory access for each of the selected plurality of memories when the variable is allocated thereto is calculated based on the number of referencing and the bit width of the variable. After that, as a target for allocating the variable, a memory that minimizes the calculated sum of the frequency of the memory access is selected.

摘要翻译： 首先，计算在行为级别电路中描述的变量的引用次数。 接下来，提取变量的位宽，并且选择能够提取所提取的位宽度的数据传送的多个存储器。 接下来，基于参考的数量和变量的位宽来计算当分配了变量时的所选择的多个存储器中的每一个的存储器访问的频率的总和。 之后，作为用于分配变量的目标，选择最小化计算出的存储器访问频率之和的存储器。

公开(公告)号：US07237220B2

公开(公告)日：2007-06-26

申请号：US11159291

申请日：2005-06-23

申请人： Osamu Ogawa ,  Dai Hattori ,  Keiichi Kurokawa ,  Masahiko Toyonaga

发明人： Osamu Ogawa ,  Dai Hattori ,  Keiichi Kurokawa ,  Masahiko Toyonaga

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A CDFG which is a graph representing calculations and a data flow included in the design specifications of a circuit is generated S101, a clock cycle required for the processing is obtained and thus an allocated resource connection graph is generated S102. When the allocated resource connection graph includes nodes to which hardware resources having the same function are allocated, a sharing edge for controlling sharing of the nodes is added between the nodes S103. A provisional layout of the allocated resource connection graph having the sharing edge added thereto is provided S104, and the nodes of the allocated resource connection graph are shared based on the layout result S105. The sharing edge is provided with attribute or weight such as attraction or repulsion. Thus, the distance between the nodes in the layout result is controlled and the degree at which the resources are shared is controlled.

摘要翻译： 产生表示电路设计规范中的计算和数据流的曲线图CD1G，获得处理所需的时钟周期，从而生成分配的资源连接图。当分配的资源 连接图包括分配了具有相同功能的硬件资源的节点，在节点S103之间添加用于控制节点共享的共享边。提供具有添加了共享边的已分配资源连接图的临时布局S 104，并且基于布局结果S 105共享所分配的资源连接图的节点。共享边缘被赋予诸如吸引力或排斥性的属性或权重。 因此，控制布局结果中的节点之间的距离，并且控制资源共享的程度。

公开(公告)号：US20050125762A1

公开(公告)日：2005-06-09

申请号：US10991052

申请日：2004-11-16

申请人： Dai Hattori ,  Osamu Ogawa ,  Keiichi Kurokawa

发明人： Dai Hattori ,  Osamu Ogawa ,  Keiichi Kurokawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： First of all, the number of referencing of a variable described in a behavior level circuit is calculated. Next, a bit width of the variable is extracted, and a plurality of memories capable of data transferring of the extracted bit width are selected. Next, a sum of a frequency of memory access for each of the selected plurality of memories when the variable is allocated thereto is calculated based on the number of referencing and the bit width of the variable. After that, as a target for allocating the variable, a memory that minimizes the calculated sum of the frequency of the memory access is selected.

摘要翻译： 首先，计算在行为级别电路中描述的变量的引用次数。 接下来，提取变量的位宽，并且选择能够提取所提取的位宽度的数据传送的多个存储器。 接下来，基于参考的数量和变量的位宽来计算当分配了变量时的所选择的多个存储器中的每一个的存储器访问的频率的总和。 之后，作为用于分配变量的目标，选择最小化计算出的存储器访问频率之和的存储器。

公开(公告)号：US08356713B2

公开(公告)日：2013-01-22

申请号：US12741168

申请日：2008-10-30

申请人： Osamu Ogawa

发明人： Osamu Ogawa

IPC分类号： B65D85/48

CPC分类号： H01L21/67369

摘要： A retainer includes a frame, a pair of first elastic parts projected from a pair of opposing parts of the frame so as to approach to each other, and a second elastic part that is supported at the bent free ends of the paired first elastic parts to hold a substrate. The outside end of the second elastic part is positioned outside the free end of the first elastic part and closer to the opposing part of the frame. Also, first and second holds for holding the rim of the substrate are formed apart from each other. The second hold is positioned on the outer end side of the second elastic part from the first hold.

摘要翻译： 保持器包括框架，从框架的一对相对部分突出以使得彼此接近的一对第一弹性部件和被支撑在成对的第一弹性部件的弯曲自由端处的第二弹性部件， 握住底物。 第二弹性部分的外端位于第一弹性部分的自由端的外侧并且更靠近框架的相对部分。 此外，用于保持基板的边缘的第一和第二保持部彼此分开地形成。 第二保持件从第一保持件定位在第二弹性部件的外端侧。

公开(公告)号：US20120269667A1

公开(公告)日：2012-10-25

申请号：US13497620

申请日：2011-08-10

申请人： Fuminori Sakima ,  Osamu Ogawa ,  Atsuo Okaichi ,  Noboru Iida ,  Shingo Oyagi

发明人： Fuminori Sakima ,  Osamu Ogawa ,  Atsuo Okaichi ,  Noboru Iida ,  Shingo Oyagi

IPC分类号： F04B17/03

CPC分类号： F04B39/04 ,  F04C18/356 ,  F04C23/008 ,  F04C23/02 ,  F04C29/0021 ,  F04C29/026 ,  F04C29/045 ,  F04C29/12 ,  F04C2240/807

摘要： A hermetic compressor (100) includes a closed casing (2), a compression mechanism (4), a motor (6), a discharge pipe (8), a first balance weight (18), a swirl flow generating portion (21), and a second balance weight (19). The motor (6) has a stator (14) and a rotor (15). A communication passage (20) is formed in the rotor (15) so as to introduce, into an upper space (7), a working fluid compressed in the compression mechanism (4) and discharged to a lower space (5) of the closed casing (2). A baffle plate (122) is provided as a discharge direction deflecting portion for causing the compressed working fluid to travel from the communication passage (20) to the upper space (7), while deflecting the working fluid in a direction inclined with respect to a direction parallel to a rotational axis O. The baffle plate (122) may be constituted by a part of the swirl flow generating portion (21).

摘要翻译： 封闭式压缩机（100）包括封闭壳体（2），压缩机构（4），马达（6），排放管（8），第一平衡重（18），涡流产生部分（21） ，和第二平衡重（19）。 电动机（6）具有定子（14）和转子（15）。 连通通道（20）形成在转子（15）中，以便在上部空间（7）中将压缩机构（4）中压缩的工作流体引入到封闭的压缩机构（4）的下部空间（5）中 套管（2）。 设置挡板（122）作为排出方向偏转部分，用于使压缩的工作流体从连通通道（20）行进到上部空间（7），同时使工作流体沿相对于 方向平行于旋转轴线O.挡板（122）可以由旋流产生部分（21）的一部分构成。

公开(公告)号：US06711452B1

公开(公告)日：2004-03-23

申请号：US09610370

申请日：2000-07-05

申请人： Osamu Ogawa

发明人： Osamu Ogawa

IPC分类号： G06F1900

CPC分类号： G03F7/70525 ,  G03F7/70508

摘要： An apparatus adapted for exposing a semiconductor is controlled by a program using a plurality of parameters. The apparatus has an extraction device that extracts a parameter, from the plurality of parameters, of which a settable range is changed due to an upgrade of the program. An edit device edits a value of an extracted parameter extracted by the extraction device.

摘要翻译： 适于暴露半导体的装置由使用多个参数的程序控制。 该装置具有从多个参数中提取参数的提取装置，其中由于程序的升级可设置范围被改变。 编辑装置编辑由提取装置提取的提取参数的值。

公开(公告)号：USD424559S

公开(公告)日：2000-05-09

申请号：US108120

申请日：1999-07-20

申请人： Osamu Ogawa

设计人： Osamu Ogawa