利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.024 秒)

    Method of making a semiconductor device with buried electrode
    3.
    发明授权
    Method of making a semiconductor device with buried electrode 失效
    制造具有埋电极的半导体器件的方法

    公开(公告)号：US5364802A

    公开(公告)日：1994-11-15

    申请号：US130461

    申请日：1993-10-01

    申请人： Yuzo Kataoka ,  Toshihiko Ichise ,  Keiji Ishizuka ,  Tetsuo Asaba

    发明人： Yuzo Kataoka ,  Toshihiko Ichise ,  Keiji Ishizuka ,  Tetsuo Asaba

    IPC分类号： H01L21/331 ,  H01L21/335 ,  H01L21/74 ,  H01L21/761 ,  H01L29/08 ,  H01L29/417

    CPC分类号： H01L29/66416 ,  H01L21/743 ,  H01L21/761 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/66272

    摘要： A semiconductor device including a bipolar transistor, has a collector region including a first semiconductor region of the first conductivity type and a second semiconductor region of the first conductivity type having higher resistance than the first semiconductor region, a base region including a semiconductor region of the second conductivity type, and an emitter region including a semiconductor region of the first conductivity type. The semiconductor device further comprises a metal layer region for connecting the first semiconductor region and the collector electrode on the collector region provided within the second semiconductor region layer of the collector region.

    摘要翻译： 包括双极晶体管的半导体器件具有包括第一导电类型的第一半导体区域和具有比第一半导体区域更高的电阻的第一导电类型的第二半导体区域的集电极区域，包括半导体区域的半导体区域的基极区域 第二导电类型和包括第一导电类型的半导体区域的发射极区域。 半导体器件还包括金属层区域，用于在设置在集电区域的第二半导体区域层内的集电极区域上连接第一半导体区域和集电极电极。

    Semiconductor device with buried electrode
    4.
    发明授权
    Semiconductor device with buried electrode 失效
    具有埋电极的半导体器件

    公开(公告)号：US5306934A

    公开(公告)日：1994-04-26

    申请号：US823604

    申请日：1992-01-17

    申请人： Yuzo Kataoka ,  Toshihiko Ichise ,  Keiji Ishizuka ,  Tetsuo Asaba

    发明人： Yuzo Kataoka ,  Toshihiko Ichise ,  Keiji Ishizuka ,  Tetsuo Asaba

    IPC分类号： H01L21/331 ,  H01L21/335 ,  H01L21/74 ,  H01L21/761 ,  H01L29/08 ,  H01L29/417 ,  H01L29/80 ,  H01L23/48

    CPC分类号： H01L29/66416 ,  H01L21/743 ,  H01L21/761 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/66272

    摘要： A semiconductor device including a bipolar transistor, has a collector region including a first semiconductor region of the first conductivity type and a second semiconductor region of the first conductivity type having higher resistance than the first semiconductor region, a base region including a semiconductor region of the second conductivity type, and an emitter region including a semiconductor region of the first conductivity type. The semiconductor device further comprises a metal layer region for connecting the first semiconductor region and the collector electrode on the collector region provided within the second semiconductor region layer of the collector region.

    摘要翻译： 包括双极晶体管的半导体器件具有包括第一导电类型的第一半导体区域和具有比第一半导体区域更高的电阻的第一导电类型的第二半导体区域的集电极区域，包括半导体区域的半导体区域的基极区域 第二导电类型和包括第一导电类型的半导体区域的发射极区域。 半导体器件还包括金属层区域，用于在设置在集电区域的第二半导体区域层内的集电极区域上连接第一半导体区域和集电极电极。

    Image signal correcting in image data processing requiring only small memory capacity
    6.
    发明授权
    Image signal correcting in image data processing requiring only small memory capacity 失效
    图像信号校正在仅需要较小存储容量的图像数据处理中

    公开(公告)号：US5262873A

    公开(公告)日：1993-11-16

    申请号：US788458

    申请日：1991-11-05

    申请人： Keiji Ishizuka

    发明人： Keiji Ishizuka

    IPC分类号： H04N1/401 ,  H04N1/40

    CPC分类号： H04N1/401

    摘要： An image signal correcting circuit device includes an A/D conversion unit for converting an analog image signal output from an image reading unit into a digital signal, a storage unit for storing correction data, and a correction unit for performing correction on a signal based on the correction data stored in the storage unit. The correction data stored in the storage unit is difference data between at least two pixel signals in the digital signal which is generated by a correction data generating unit. Alternatively, the correction data stored in the storage unit is obtained by amplifying an analog reference signal by an amplification factor of m (m>1) and by converting the amplified analog signal into a digital correction signal by the A/D conversion unit.

    Arithmetic encoding with carry over processing
    7.
    发明授权
    Arithmetic encoding with carry over processing 失效
    具有结转处理的算术编码

    公开(公告)号：US5784497A

    公开(公告)日：1998-07-21

    申请号：US611497

    申请日：1996-03-06

    申请人： Keiji Ishizuka ,  Atsushi Furuya

    发明人： Keiji Ishizuka ,  Atsushi Furuya

    IPC分类号： H03M7/40 ,  H04N1/417 ,  G06K9/36 ,  G06K9/46

    CPC分类号： H04N1/417 ,  H03M7/4006

    摘要： An image encoding device for effecting the carryover process on a real-time basis in arithmetic encoding, and without interruption in the function of the arithmetic encoder. The device is provided with an encoder for outputting code data, encoded by arithmetic codes, in succession by a predetermined number of bits, shift registers for retaining plural sets of the code data output from the encoder, and a processor for applying a carry-over process to the thus retained plural sets of code data.

    摘要翻译： 一种图像编码装置，用于在算术编码中实时实现携带处理，并且不会中断算术编码​​器的功能。 该装置设置有用于输出由算术代码编码的代码数据的编码器，连续地以预定数量的位输出，用于保存从编码器输出的多组代码数据的移位寄存器和用于应用结转的处理器 处理到如此保留的多组代码数据。

    Coding method and apparatus therefor
    8.
    发明授权
    Coding method and apparatus therefor 失效
    编码方法及其装置

    公开(公告)号：US5655032A

    公开(公告)日：1997-08-05

    申请号：US515385

    申请日：1995-08-15

    申请人： Hidefumi Ohsawa ,  Keiji Ishizuka

    发明人： Hidefumi Ohsawa ,  Keiji Ishizuka

    IPC分类号： G06T9/00 ,  H04N1/417

    CPC分类号： G06T9/004 ,  H04N1/4172

    摘要： The present invention discloses a method and apparatus for hierarchical coding of image data using a typical prediction TP if a 2.times.2 array of pixels can be reduced to coded pixel. The present invention uses a TP flag, TP discrimination and a two line delay. Accordingly, the hierarchical coding can be realized by a small amount of hardware. According to deterministic prediction DP, if there is a decision that the image data may be reduced then the value of the pixel can be predicted from a reduced pixel (low resolution data) and surrounding pixels (high resolution data) which are extracted in advance. If the pixel to be coded is one that can be uniquely determined this pixel is excluded form coding.

    摘要翻译： 本发明公开了一种用于使用典型预测TP对图像数据进行分层编码的方法和装置，如果可将2×2像素阵列减少为编码像素。 本发明使用TP标志，TP鉴别和两行延迟。 因此，可以通过少量的硬件来实现层次编码。 根据确定性预测DP，如果存在可以减少图像数据的决定，则可以从预先提取的缩小像素（低分辨率数据）和周围像素（高分辨率数据）预测像素的值。 如果要编码的像素是可以被唯一确定的像素，则将该像素排除在编码之外。

    Decoding apparatus and method
    9.
    发明授权
    Decoding apparatus and method 有权
    解码装置和方法

    公开(公告)号：US06313767B1

    公开(公告)日：2001-11-06

    申请号：US09503591

    申请日：2000-02-14

    申请人： Keiji Ishizuka ,  Tetsuya Tateno ,  Koji Aoki

    发明人： Keiji Ishizuka ,  Tetsuya Tateno ,  Koji Aoki

    IPC分类号： H03M740

    CPC分类号： H03M7/425

    摘要： A decoding apparatus which efficiently stores information to determine an address value to read a decoded value from a decoded value memory. The apparatus performs decoding processing at a high speed, and further, reduces the memory capacity. The apparatus comprises a first storage for continuously storing decoded values for variable-length codes of the same code length; a second storage for storing an initial address in the first storage; a third storage for storing offset values between the initial address in the first storage and addresses for storing decoded values for variable-length codes of respective code lengths, respectively; a first specification unit for specifying a code length of an input variable-length code; a second specification unit for specifying the order of the input variable-length code among variable-length codes belonging to the specified code length; and an address generator for generating an address to read a decoded value from the first storage, based on the offset value corresponding to the code length specified by the first specification unit and the order specified by the second specification unit.

    摘要翻译： 一种解码装置，其有效地存储用于确定从解码值存储器读取解码值的地址值的信息。 该装置以高速进行解码处理，进一步降低存储容量。 该装置包括用于连续存储具有相同码长的可变长度码的解码值的第一存储器; 用于在第一存储器中存储初始地址的第二存储器; 用于存储第一存储器中的初始地址之间的偏移值的第三存储器和用于分别存储用于代码长度可变长度代码的解码值的地址; 用于指定输入可变长度代码的代码长度的第一指定单元; 第二规格单元，用于指定属于指定代码长度的可变长度代码之间的输入可变长度代码的顺序; 以及地址发生器，用于基于与由第一指定单元指定的代码长度和由第二指定单元指定的顺序相对应的偏移值，生成从第一存储器读取解码值的地址。

    Coding method and apparatus therefor
    10.
    发明授权
    Coding method and apparatus therefor 失效
    编码方法及其装置

    公开(公告)号：US6026197A

    公开(公告)日：2000-02-15

    申请号：US736942

    申请日：1996-10-25

    申请人： Hidefumi Ohsawa ,  Keiji Ishizuka

    发明人： Hidefumi Ohsawa ,  Keiji Ishizuka

    IPC分类号： G06T9/00 ,  H04N1/417 ,  G06K9/46

    CPC分类号： G06T9/004 ,  H04N1/4172

    摘要： There is provided a coding apparatus and method for hierarchically coding an image, in which a number of consecutive lines of image data representing pixels of the image are entered line by line. Reduced image data representing pixels of a reduced image based on the entered image data are formed. A determination is made in parallel with the formation of the reduced image data as to whether or not image data of an object pixel to be coded can be predicted from the reduced image data and from image data representing surrounding pixels of the entered object pixel. The entered image data are coded in accordance with the determination result.

    摘要翻译： 提供了一种用于对图像进行分层编码的编码装置和方法，其中表示图像的像素的图像数据的连续行数被逐行输入。 形成基于输入的图像数据来表示缩小图像的像素的缩小图像数据。 与缩小图像数据的形成是否可以从缩小图像数据中预测要编码的对象像素的图像数据以及表示输入的对象像素的周围像素的图像数据的平行进行确定。 输入的图像数据根据确定结果进行编码。