公开(公告)号：US06816952B1

公开(公告)日：2004-11-09

申请号：US10160947

申请日：2002-05-31

申请人： Kelvin S. Vartti ,  Wayne D. Ward ,  Hans C. Mikkelsen

发明人： Kelvin S. Vartti ,  Wayne D. Ward ,  Hans C. Mikkelsen

IPC分类号： G06F1214

CPC分类号： G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0815 ,  G06F12/0862

摘要： The current invention provides an improved system and method for locking shared resources. The invention may operate in a data processing environment including a main memory system coupled to multiple instruction processors (IPs). Lock-type instructions are included within the hardware instruction set of ones of the IPs. These lock-type instructions are executed to gain access to a software-lock stored at a predetermined location within the main memory. After activating the software-lock, further, indivisible execution of the lock-type instruction causes one or more addresses associated with the software-lock to be retrieved. These addresses are used as pointers to, in turn, retrieve the data signals protected by the software-lock. Requests for the protected data signals are issued automatically by the hardware on behalf of the requesting IP, and the IP is allowed to continue instruction execution.

摘要翻译： 本发明提供了一种用于锁定共享资源的改进的系统和方法。 本发明可以在包括耦合到多个指令处理器（IP）的主存储器系统的数据处理环境中操作。 锁定指令包含在IP的硬件指令集中。 执行这些锁定型指令以访问存储在主存储器内的预定位置处的软件锁。 在激活软件锁定之后，进一步地，锁定型指令的不可分割的执行导致与软件锁相关联的一个或多个地址被检索。 这些地址用作指针，反过来检索由软件锁定保护的数据信号。 受保护的数据信号的请求由硬件代表请求的IP自动发出，并且允许IP继续执行指令。

公开(公告)号：US06601153B1

公开(公告)日：2003-07-29

申请号：US09476022

申请日：1999-12-31

申请人： Kenneth L. Engelbrecht ,  Hans C. Mikkelsen ,  Wayne D. Ward

发明人： Kenneth L. Engelbrecht ,  Hans C. Mikkelsen ,  Wayne D. Ward

IPC分类号： G06F9312

CPC分类号： G06F12/08 ,  G06F12/0891 ,  Y10S707/99953

摘要： A system and method for increasing processing performance in a computer system by asynchronously performing system activities that do not conflict with normal instruction processing, during inactive memory access periods. The computer system includes at least one instruction processor to process instructions of an instruction stream, and a memory to store data. One or more inactive data blocks in the memory are identified, and a list of addresses corresponding to the identified inactive data blocks is generated. Available computing cycles occurring during processing in the computer system are identified, such as processing stalls and idle memory write periods. The inactive data blocks associated with the list of addresses are initialized to a predetermined state, during the available computing cycles. Addresses corresponding to those initialized data blocks are then made available to the computing system to facilitate use of the data blocks.

摘要翻译： 一种通过在非活动存储器访问期间异步执行不与正常指令处理冲突的系统活动来提高计算机系统中的处理性能的系统和方法。 计算机系统包括处理指令流的指令的至少一个指令处理器和存储数据的存储器。 识别存储器中的一个或多个非活动数据块，并且生成与所识别的非活动数据块相对应的地址列表。 识别在计算机系统中处理期间发生的可用计算周期，例如处理停顿和空闲存储器写入周期。 在可用的计算周期期间将与地址列表相关联的非活动数据块初始化为预定状态。 然后使与这些初始化的数据块相对应的地址可用于计算系统以便于使用数据块。

公开(公告)号：US6029205A

公开(公告)日：2000-02-22

申请号：US800344

申请日：1997-02-14

申请人： Merwin H. Alferness ,  Mark D. Aubel ,  Charles R. Caldarale ,  James W. Douglas ,  David C. Johnson ,  David R. Johnson ,  Joseph P. Kerzman ,  James R. McBreen ,  Hans C. Mikkelsen ,  Donna J. Plunkett ,  Richard M. Shelton ,  Francis A. Stephens ,  Wayne D. Ward

发明人： Merwin H. Alferness ,  Mark D. Aubel ,  Charles R. Caldarale ,  James W. Douglas ,  David C. Johnson ,  David R. Johnson ,  Joseph P. Kerzman ,  James R. McBreen ,  Hans C. Mikkelsen ,  Donna J. Plunkett ,  Richard M. Shelton ,  Francis A. Stephens ,  Wayne D. Ward

IPC分类号： G06F9/46 ,  G06F15/163

CPC分类号： G06F9/546

摘要： A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transferred from a sending process to a receiving process is stored in a queue entry which is visible in the virtual address space of the first process. The queue entry is added to a queue by the sending process directing the processor to execute an enqueue instruction. The receiving process removes the queue entry from the queue by directing the processor to execute a dequeue instruction. The receiving process then has direct access and visibility to the contents of the queue entry without having to copy the data into its virtual address space. Instead of sending data in a queue entry, a sending process may send an event indicator and no data. The receiving process may then wait on an empty queue until an event notification is received in a queue entry enqueued to the queue. Protection is provided by the system to prevent unauthorized access to the queue by other processes active in the system.

摘要翻译： 用于数字计算机系统中的并行执行，协作顺序处理之间的进程间通信的系统和方法使用共享存储器队列作为消息传递和过程同步的机制。 要从发送进程传送到接收进程的数据存储在第一进程的虚拟地址空间中可见的队列条目中。 发送进程将队列条目添加到队列中，该进程指示处理器执行入队指令。 接收进程通过指示处理器执行出队指令来从队列中移除队列条目。 然后，接收过程对队列条目的内容具有直接访问和可见性，而不必将数据复制到其虚拟地址空间中。 发送进程可以发送一个事件指示符而不是数据，而不是在队列条目中发送数据。 然后，接收进程可以等待一个空队列，直到在排入队列的队列中接收到一个事件通知。 系统提供保护，以防止系统中其他进程未经授权的访问队列。

公开(公告)号：US5602998A

公开(公告)日：1997-02-11

申请号：US362638

申请日：1994-12-22

申请人： Merwin H. Alferness ,  Charles R. Caldarale ,  David C. Johnson ,  David R. Johnson ,  James R. McBreen ,  Wayne D. Ward

发明人： Merwin H. Alferness ,  Charles R. Caldarale ,  David C. Johnson ,  David R. Johnson ,  James R. McBreen ,  Wayne D. Ward

IPC分类号： G06F9/46

CPC分类号： G06F9/544 ,  G06F9/546

摘要： A system and method for removing a queue entry containing message data from a queue shared by communicating, sequential processes includes dequeue (DEQ) and dequeue or wait (DEQW) instructions. The dequeue instruction removes a queue entry from the head of the shared queue, thereby providing access to the message data contained in the queue entry to the dequeuing process. The dequeue or wait instruction removes a queue entry from the shared queue if there is one, otherwise it suspends the execution of the dequeuing process until an entry is enqueued to the queue. If an event is selected by the dequeuing process, the dequeuing process is suspended until notification of the event is detected in the shared queue. Execution of the dequeue and dequeue or wait instructions include blocking access to the queue by other processes, updating queue linkages, deactivating processes waiting on entries or events being made to the queue, monitoring interrupts, and validating the appropriate queue data structures.

摘要翻译： 用于从通过通信的顺序进程共享的队列中去除包含消息数据的队列条目的系统和方法包括出队（DEQ）和出队或等待（DEQW）指令。 出队指令从共享队列的头部移除队列条目，从而提供对包含在队列进入出队进程的消息数据的访问。 如果有一个，出队或等待指令将从共享队列中移除一个队列条目，否则将暂停执行出队进程，直到一个条目排入队列。 如果由出队进程选择了一个事件，则在共享队列中检测到事件的通知之前暂停出队进程。 执行出队和出队或等待指令包括阻止其他进程对队列的访问，更新队列链接，停用等待队列进入的进程，监视中断和验证适当的队列数据结构。

公开(公告)号：US06922744B1

公开(公告)日：2005-07-26

申请号：US09925592

申请日：2001-08-09

申请人： Ralph E. Sipple ,  Wayne D. Ward

发明人： Ralph E. Sipple ,  Wayne D. Ward

IPC分类号： G06F12/08 ,  G06F12/14

CPC分类号： G06F12/0817

摘要： In order to implement alternative pathways and procedures for handling a separate set of software locks, an arrangement of circuits is described. These circuits allow for generating and handling specific requests for communal software locks without additional software development through pathways and procedures separate from ordinary lock handling operations. A side door communications pathway is set up to handle the communal locks separately from the ordinary data transfer pathways through which ordinary software locks get handled. Supporting and controller circuits handle the locking and unlocking process as well as communicating results of lock requests back to requesters.

摘要翻译： 为了实现用于处理单独的软件锁集合的替代路径和过程，描述了电路的布置。 这些电路允许生成和处理公共软件锁的特定请求，而无需通过与普通锁操作操作分离的路径和过程进行额外的软件开发。 侧门通信路径被设置为与普通软件锁处理的普通数据传输路径分开处理公用锁。 支持和控制器电路处理锁定和解锁过程，并将锁定请求的结果传达给请求者。

公开(公告)号：US06654875B1

公开(公告)日：2003-11-25

申请号：US09572511

申请日：2000-05-17

申请人： Thomas D. Hartnett ,  John S. Kuslak ,  Peter B. Criswell ,  Wayne D. Ward

发明人： Thomas D. Hartnett ,  John S. Kuslak ,  Peter B. Criswell ,  Wayne D. Ward

IPC分类号： G06F930

CPC分类号： G06F9/30189 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/382 ,  G06F9/3867

摘要： Instruction processor and method supporting dual-mode execution of computer instructions. In various embodiments, certain instructions are executable in one of two modes. The first mode is compatible with the native instruction set and data words, and the second mode is an adaptation suitable for platform independent instructions. A control word RAM is addressed by the operation code of an instruction, and each word in the control word RAM includes an address into a microcode RAM. The address into the microcode RAM is manipulated in accordance with the various embodiments to reference either a first set of microcode for native instructions and data words, or a second set of microcode for execution in a platform-independent mode.

摘要翻译： 指令处理器和方法支持双模式执行计算机指令。 在各种实施例中，某些指令可以以两种模式之一执行。 第一种模式与本机指令集和数据字兼容，第二种模式是适合平台无关指令的适配。 控制字RAM由指令的操作码寻址，并且控制字RAM中的每个字都包括到微码RAM中的地址。 根据各种实施例，对微代码RAM的地址进行操作以引用用于本地指令和数据字的第一组微代码，或者以与平台无关的模式来执行的第二组微代码。

公开(公告)号：US06247064B1

公开(公告)日：2001-06-12

申请号：US08361626

申请日：1994-12-22

申请人： Merwin H. Alferness ,  Charles R. Caldarale ,  David C. Johnson ,  David R. Johnson ,  James R. McBreen ,  Wayne D. Ward

发明人： Merwin H. Alferness ,  Charles R. Caldarale ,  David C. Johnson ,  David R. Johnson ,  James R. McBreen ,  Wayne D. Ward

IPC分类号： G06F900

CPC分类号： G06F9/546

摘要： A system and method for adding a queue entry containing message data to a queue shared by communicating, sequential processes includes an enqueue instruction. The enqueue instruction attaches a queue entry to either the tail or the head of the shared queue, as specified by an application programmer. Execution of the enqueue instruction includes blocking access to the queue by other processes, updating queue linkages, activating processes waiting on entries being made to the queue, monitoring interrupts, and validating the appropriate queue data structures. If desired, in lieu of adding a queue entry containing message data to the queue, the enqueue instruction inserts an event indicator into the shared queue structure, thereby providing synchronization capabilities between communicating processes.

摘要翻译： 将包含消息数据的队列条目添加到通过通信，顺序进程共享的队列的系统和方法包括入队指令。 入队指令将队列条目附加到应用程序员指定的共享队列的尾部或头部。 执行入站指令包括阻止其他进程对队列的访问，更新队列链接，激活等待队列进入的进程，监视中断以及验证适当的队列数据结构。 如果需要，代替将包含消息数据的队列条目添加到队列中，入队指令将事件指示符插入到共享队列结构中，从而在通信进程之间提供同步能力。

公开(公告)号：US06944863B1

公开(公告)日：2005-09-13

申请号：US09747036

申请日：2000-12-21

申请人： Wayne D. Ward ,  David R. Johnson ,  David C. Johnson ,  Charles R. Caldarale

发明人： Wayne D. Ward ,  David R. Johnson ,  David C. Johnson ,  Charles R. Caldarale

IPC分类号： G06F7/00 ,  G06F9/46 ,  G06F15/163

CPC分类号： G06F9/546 ,  G06F9/526 ,  G06F9/544 ,  G06F2209/522 ,  G06F2209/548

摘要： In a computer system a system of exchanging tokens for queue banks is created that permits a requester to directly specify which queue bank is wanted. Only the desired queue bank is withdrawn from a queue bank repository to accomplish this and no sorting or FIFO handling of queue banks is needed. The system uses a schema similar to a coat check room, where the requester is given a token when the requestor wants to deposit a queue bank into the queue bank repository. The queue bank repository returns the queue bank when the token is returned by the requester. In its most efficient form, two machine-level instructions handle the entire operation, a withdraw instruction and a deposit instruction.

摘要翻译： 在计算机系统中，创建用于队列的交换令牌的系统，其允许请求者直接指定哪个队列被想要。 只有期望的队列从队列库存储库中撤出才能完成，并且不需要排队或FIFO处理队列。 系统使用类似于外套检查室的架构，当请求者希望将队列存入队列库存储库时，请求者被给予令牌。 当请求者返回令牌时，队列库存储库返回队列。 在其最有效的形式中，两个机器级指令处理整个操作，撤销指令和存款指令。

公开(公告)号：US06986003B1

公开(公告)日：2006-01-10

申请号：US09927069

申请日：2001-08-09

申请人： Ralph E. Sipple ,  Wayne D. Ward

发明人： Ralph E. Sipple ,  Wayne D. Ward

IPC分类号： G06F12/08 ,  G06F12/14

CPC分类号： G06F12/0815 ,  G06F9/526 ,  G06F12/0811 ,  G06F12/0875

摘要： Multi-processor computer systems with multiple levels of cache memories are slowed down in trying to process software locks for common functions. This invention obviates the problem for the vast majority of transactions by providing an alternate procedure for handling so-called communal locks differently from ordinary software locks. The alternative procedure is not used for ordinary (non communal software lock) data and instruction transfers. The function of the CSWL (Communal SoftWare Lock) is actually accomplished at a specific cache to which an individual CSWL is mapped to, rather than sending the lock to the requesting process, which also enhances efficiency.

摘要翻译： 具有多级高速缓存存储器的多处理器计算机系统在尝试处理常用功能的软件锁时放慢速度。 本发明通过提供与普通软件锁不同的方式处理所谓的公用锁的替代过程来消除绝大多数事务的问题。 替代程序不用于普通（非公用软件锁）数据和指令传输。 CSWL（公共软件锁）的功能实际上是在单个CSWL映射到的特定高速缓存上实现的，而不是将锁发送到请求进程，这也提高了效率。

公开(公告)号：US06810464B1

公开(公告)日：2004-10-26

申请号：US09925384

申请日：2001-08-09

申请人： Ralph E. Sipple ,  Wayne D. Ward

发明人： Ralph E. Sipple ,  Wayne D. Ward

IPC分类号： G06F1200

CPC分类号： G06F9/52 ,  G06F12/0806 ,  Y10S707/99938

摘要： Multi-processor computer systems with multiple levels of cache memories are given an alternate pathway for handling highly contended-for locks. These are called communal locks. The alternate pathway allows for alternate processing schemas that do not impede the performance of the overall system as is otherwise the case in such computer systems where contended-for locks bounce back and forth between contending caches, crimping storage bus bandwidth and system performance. The alternative pathway is not used for ordinary (non communal software lock) data and instruction transfers.

摘要翻译： 具有多级高速缓冲存储器的多处理器计算机系统被给予用于处理高度争议的锁的备选路径。 这些被称为公共锁。 备用路径允许不妨碍整个系统的性能的替代处理模式，否则在这样的计算机系统中，竞争对手的锁定在竞争缓存之间反弹，压缩存储总线带宽和系统性能的计算机系统的情况。 替代途径不用于普通（非公共软件锁）数据和指令传输。