专利检索 ap:("Keng L. Wong" OR "Niraj Bindal" OR "Hong-Piao Ma" OR "George Geannopoulos" OR "Greg F. Taylor" OR "Edward A. Burton") AND inv:"Niraj Bindal" 第 1 页

1.

发明授权
Clock generating circuit and method 失效

公开(公告)号：US06985041B2

公开(公告)日：2006-01-10

申请号：US10136390

申请日：2002-05-02

申请人： Keng L. Wong , Niraj Bindal , Hong-Piao Ma , George Geannopoulos , Greg F. Taylor , Edward A. Burton

发明人： Keng L. Wong , Niraj Bindal , Hong-Piao Ma , George Geannopoulos , Greg F. Taylor , Edward A. Burton

IPC分类号： H03B27/00

CPC分类号： G06F1/10 , H03K3/0315 , H03K5/133 , H03K5/15013

摘要： A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.