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50 条记录 (耗时 0.03 秒)

    Voltage control for clock generating circuit
    5.
    发明授权
    Voltage control for clock generating circuit 有权
    时钟发生电路的电压控制

    公开(公告)号：US07242261B2

    公开(公告)日：2007-07-10

    申请号：US10680498

    申请日：2003-10-06

    申请人： Keng L. Wong ,  Hong-Piao Ma ,  Greg F. Taylor

    发明人： Keng L. Wong ,  Hong-Piao Ma ,  Greg F. Taylor

    IPC分类号： H03B1/00

    CPC分类号： H03K5/15013 ,  G06F1/10 ,  G06F1/28 ,  H03K3/011 ,  H03K3/0315 ,  H03K5/133

    摘要： An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.

    摘要翻译： 提供了一种装置，其包括时钟分配网络，围绕时钟分配网络设置的多个分布式振荡器，以便在时钟分配网络上提供时钟信号;以及功率控制电路，用于控制施加到多个分布式振荡器的功率。 功率控制电路包括用于基于期望功率电平产生参考电压的带隙装置和用于从带隙装置接收参考电压并且从设备外部的源接收电压信号的比较/判定装置。 比较/判定装置确定从电源接收的信号是否对应于期望的功率电平。

    Voltage control for clock generating circuit
    6.
    发明授权
    Voltage control for clock generating circuit 有权

    公开(公告)号：US06778033B2

    公开(公告)日：2004-08-17

    申请号：US10136318

    申请日：2002-05-02

    申请人： Keng L. Wong ,  Hong-Piao Ma ,  Greg F. Taylor

    发明人： Keng L. Wong ,  Hong-Piao Ma ,  Greg F. Taylor

    IPC分类号： H03B100

    CPC分类号： H03K5/15013 ,  G06F1/10 ,  G06F1/28 ,  H03K3/011 ,  H03K3/0315 ,  H03K5/133

    摘要： An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.

    Method and apparatus for deskewing clock signals
    7.
    发明授权
    Method and apparatus for deskewing clock signals 失效
    用于校正时钟信号的方法和装置

    公开(公告)号：US6075832A

    公开(公告)日：2000-06-13

    申请号：US946671

    申请日：1997-10-07

    申请人： George Geannopoulos ,  Keng L. Wong ,  Greg F. Taylor ,  Xia Dai

    发明人： George Geannopoulos ,  Keng L. Wong ,  Greg F. Taylor ,  Xia Dai

    IPC分类号： G06F1/10 ,  H03D3/24 ,  H03D13/00 ,  H03L7/00 ,  H03L7/081 ,  H03L7/087

    CPC分类号： H03L7/087 ,  G06F1/10 ,  H03L7/0814

    摘要： An apparatus for deskewing clock signals in a synchronous digital system. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates an output based on a phase relationship between those clock signals. A controller then receives the output of the phase detector and determines which one of the plurality of clock signals requires adjustment based on the output of the phase detector and a bit from a delay shift register. The controller transmits a delay signal to one of a plurality of delay circuits which modifies the delay of the clock signal that the controller determined to require adjustment.

    摘要翻译： 一种在同步数字系统中对时钟信号进行偏移校正的装置。 该装置包含相位检测电路，其接收多个时钟信号，并根据这些时钟信号之间的相位关系产生输出。 然后，控制器接收相位检测器的输出，并且基于相位检测器的输出和来自延迟移位寄存器的位确定多个时钟信号中的哪一个需要调整。 控制器将延迟信号发送到多个延迟电路中的一个，其修改控制器确定需要调整的时钟信号的延迟。

    Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise
    8.
    发明授权
    Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise 失效
    优化时钟分配的方法和装置，以减少电源噪声的影响

    公开(公告)号：US06934872B2

    公开(公告)日：2005-08-23

    申请号：US10021058

    申请日：2001-12-19

    申请人： Keng L. Wong ,  Hung-Piao Ma ,  Tawfik M. Rahal-Arabi ,  Javed Barkatullah ,  Edward A. Burton

    发明人： Keng L. Wong ,  Hung-Piao Ma ,  Tawfik M. Rahal-Arabi ,  Javed Barkatullah ,  Edward A. Burton

    IPC分类号： G06F1/10 ,  G06F1/04 ,  G06F17/50

    CPC分类号： G06F1/10

    摘要： A method and apparatus for optimizing clock distribution in a circuit to reduce the effect of power supply noise. Parameters are determined including: a response curve of a power source for a circuit, a delay sensitivity of a clock net in the circuit to the power source, a delay sensitivity of a data net in the circuit to the power source, a data delay for the data net, and a clock delay for the clock net. The clock delay is adjusted to reduce the effect of power supply noise on the data net. The adjusting is based on the response curve of the power source, the delay sensitivity of the clock net, the delay sensitivity of the data net, the data delay, and the clock delay. The adjusting includes adding a pre-distribution clock delay.

    摘要翻译： 一种用于优化电路中的时钟分布以减少电源噪声的影响的方法和装置。 确定参数，包括：电路的电源的响应曲线，到电源的电路中的时钟网络的延迟灵敏度，电路中的数据网到电源的延迟灵敏度，数据延迟 数据网和时钟网的时钟延迟。 调整时钟延迟以减少电源噪声对数据网的影响。 调整是基于电源的响应曲线，时钟网络的延迟灵敏度，数据网络的延迟灵敏度，数据延迟和时钟延迟。 调整包括添加预分配时钟延迟。

    Phase-locked loop having dynamically adjustable up/down pulse widths
    9.
    发明授权
    Phase-locked loop having dynamically adjustable up/down pulse widths 有权
    锁相环具有动态可调节的上/下脉冲宽度

    公开(公告)号：US07404099B2

    公开(公告)日：2008-07-22

    申请号：US10918301

    申请日：2004-08-13

    申请人： Mingwei Huang ,  Keng L. Wong ,  Raymond (Hon-Mo) Law ,  Chi-Yeu Chao

    发明人： Mingwei Huang ,  Keng L. Wong ,  Raymond (Hon-Mo) Law ,  Chi-Yeu Chao

    IPC分类号： G06F1/00 ,  G06F1/12 ,  G06F1/04

    CPC分类号： H03L7/0891 ,  H03L7/10

    摘要： According to embodiments of the present invention, a phase-locked loop (PLL) may include circuitry to select a wide pulse width for the phase-frequency detector control signal when the PLL is in a frequency acquisition stage, a narrow pulse width for the phase-frequency detector control signal when the PLL is in a phase capture stage, and a wide pulse width of the phase-frequency detector control signal when the PLL is in a lock stage.

    摘要翻译： 根据本发明的实施例，锁相环（PLL）可以包括当PLL处于频率采集级时为相位 - 频率检测器控制信号选择宽脉冲宽度的电路，用于相位的窄脉冲宽度 当PLL处于锁相阶段时，PLL处于相位捕获级中的频率检测器控制信号，以及相位 - 频率检测器控制信号的宽脉冲宽度。

    Delay element calibration
    10.
    发明授权
    Delay element calibration 失效
    延迟元件校准

    公开(公告)号：US07024324B2

    公开(公告)日：2006-04-04

    申请号：US10856907

    申请日：2004-05-27

    申请人： Michael C. Rifani ,  Keng L. Wong ,  Christopher Pan

    发明人： Michael C. Rifani ,  Keng L. Wong ,  Christopher Pan

    IPC分类号： G06F19/00

    CPC分类号： G01R29/0273

    摘要： A method for calibrating a delay element is described herein. In some embodiments, the method may include generating a clock signal with a clock edge, generating a reference signal with a reference edge using an adjustable delay line to delay the clock signal, and delaying a selected one of the clock signal and the reference signal through an array delay line having an array delay element with an array delay. In some embodiments, the method may further include adjusting the adjustable delay line to obtain a first adjustable delay so that the clock and reference edges are aligned on one side of the array delay element, adjusting the adjustable delay line to obtain a second adjustable delay so that the clock and reference edges are aligned on the other side of the array delay element, and ascertaining a delay difference between the first and the second adjustable delays to determine a value of the array delay provided by the array delay element. Other embodiments of the present invention may include, but are not limited to, apparatuses and systems adapted to facilitate practice of the above-described method.

    摘要翻译： 本文描述了用于校准延迟元件的方法。 在一些实施例中，该方法可以包括用时钟沿生成时钟信号，使用可调延迟线产生具有参考边沿的参考信号以延迟时钟信号，以及延迟选定的一个时钟信号和参考信号通过 具有阵列延迟的阵列延迟元件的阵列延迟线。 在一些实施例中，该方法还可以包括调整可调延迟线以获得第一可调延迟，使得时钟和参考边沿在阵列延迟元件的一侧对准，调节可调延迟线以获得第二可调延迟 时钟和参考边沿在阵列延迟元件的另一侧对准，并且确定第一和第二可调延迟之间的延迟差以确定由阵列延迟元件提供的阵列延迟的值。 本发明的其它实施例可以包括但不限于适于促进实施上述方法的装置和系统。