Voltage control oscillator and quadrature modulator
    1.
    发明授权
    Voltage control oscillator and quadrature modulator 有权
    电压控制振荡器和正交调制器

    公开(公告)号:US08797108B2

    公开(公告)日:2014-08-05

    申请号:US13368069

    申请日:2012-02-07

    IPC分类号: H03B27/00 H03B5/12

    摘要: A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor; and a second capacitor.

    摘要翻译: 电压控制振荡器包括:第一和第二场效应晶体管,其中一个的漏极连接到另一个的栅极,另一个的漏极连接到该栅极; 第三和第四场效应晶体管,其中一个的漏极连接到另一个的栅极,另一个的漏极连接到该栅极; 连接在第一场效应晶体管的漏极和第二场效应晶体管的漏极之间的第一电感器; 连接在第三场效应晶体管的漏极和第四场效应晶体管的漏极之间的第二电感器; 第三电感器,其磁耦合到所述第一电感器; 磁耦合到第二电感器的第四电感器; 第一电容器; 和第二电容器。

    Voltage control oscillator and quadrature modulator
    2.
    发明授权
    Voltage control oscillator and quadrature modulator 有权
    电压控制振荡器和正交调制器

    公开(公告)号:US08134421B2

    公开(公告)日:2012-03-13

    申请号:US12783345

    申请日:2010-05-19

    摘要: A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor that capacitively couples one end of the third inductor and one end of the fourth inductor; and a second capacitor that capacitively couples the other end of the third inductor and the other end of the fourth inductor.

    摘要翻译: 电压控制振荡器包括:第一和第二场效应晶体管,其中一个的漏极连接到另一个的栅极,另一个的漏极连接到该栅极; 第三和第四场效应晶体管,其中一个的漏极连接到另一个的栅极,另一个的漏极连接到该栅极; 连接在第一场效应晶体管的漏极和第二场效应晶体管的漏极之间的第一电感器; 连接在第三场效应晶体管的漏极和第四场效应晶体管的漏极之间的第二电感器; 第三电感器,其磁耦合到所述第一电感器; 磁耦合到第二电感器的第四电感器; 第一电容器,电容耦合第三电感器的一端和第四电感器的一端; 以及电容耦合第三电感器的另一端和第四电感器的另一端的第二电容器。

    Cascoded circuit
    3.
    发明授权
    Cascoded circuit 有权
    Cascoded电路

    公开(公告)号:US07847638B2

    公开(公告)日:2010-12-07

    申请号:US12244458

    申请日:2008-10-02

    IPC分类号: H03F3/04

    摘要: A cascoded current-mirror circuit includes a first N channel MOS transistor, a second N channel MOS transistor, a third N channel MOS transistor and a fourth N channel MOS transistor. The first N channel MOS transistor and the second N channel MOS transistor are cascode-connected between a higher voltage source and a lower voltage source. The third N channel MOS transistor and the fourth N channel MOS transistor are cascode-connected between the higher voltage source and the lower voltage source. A drain of the first N channel MOS transistor is connected to gates of the first N channel MOS transistor, the second N channel MOS transistor, the third N channel MOS transistor and the fourth N channel MOS transistor. The threshold voltages of the second N channel MOS transistor and the fourth N channel MOS transistor are larger than those of the first N channel MOS transistor and the third N channel MOS transistor.

    摘要翻译: 级联电流镜电路包括第一N沟道MOS晶体管,第二N沟道MOS晶体管,第三N沟道MOS晶体管和第四N沟道MOS晶体管。 第一N沟道MOS晶体管和第二N沟道MOS晶体管被共源共栅连接在较高电压源和较低电压源之间。 第三N沟道MOS晶体管和第四N沟道MOS晶体管被共源共栅连接在较高电压源和较低电压源之间。 第一N沟道MOS晶体管的漏极连接到第一N沟道MOS晶体管,第二N沟道MOS晶体管,第三N沟道MOS晶体管和第四N沟道MOS晶体管的栅极。 第二N沟道MOS晶体管和第四N沟道MOS晶体管的阈值电压大于第一N沟道MOS晶体管和第三N沟道MOS晶体管的阈值电压。