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公开(公告)号：US08134421B2
公开(公告)日：2012-03-13
申请号：US12783345
申请日：2010-05-19
CPC分类号： H03B27/00 , H03B5/1212 , H03B5/1215 , H03B5/1225 , H03B5/1228 , H03B5/1243 , H03B5/1296
摘要： A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor that capacitively couples one end of the third inductor and one end of the fourth inductor; and a second capacitor that capacitively couples the other end of the third inductor and the other end of the fourth inductor.
摘要翻译： 电压控制振荡器包括：第一和第二场效应晶体管，其中一个的漏极连接到另一个的栅极，另一个的漏极连接到该栅极; 第三和第四场效应晶体管，其中一个的漏极连接到另一个的栅极，另一个的漏极连接到该栅极; 连接在第一场效应晶体管的漏极和第二场效应晶体管的漏极之间的第一电感器; 连接在第三场效应晶体管的漏极和第四场效应晶体管的漏极之间的第二电感器; 第三电感器，其磁耦合到所述第一电感器; 磁耦合到第二电感器的第四电感器; 第一电容器，电容耦合第三电感器的一端和第四电感器的一端; 以及电容耦合第三电感器的另一端和第四电感器的另一端的第二电容器。
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公开(公告)号：US08797108B2
公开(公告)日：2014-08-05
申请号：US13368069
申请日：2012-02-07
CPC分类号： H03B27/00 , H03B5/1212 , H03B5/1215 , H03B5/1225 , H03B5/1228 , H03B5/1243 , H03B5/1296
摘要： A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor; and a second capacitor.
摘要翻译： 电压控制振荡器包括：第一和第二场效应晶体管，其中一个的漏极连接到另一个的栅极，另一个的漏极连接到该栅极; 第三和第四场效应晶体管，其中一个的漏极连接到另一个的栅极，另一个的漏极连接到该栅极; 连接在第一场效应晶体管的漏极和第二场效应晶体管的漏极之间的第一电感器; 连接在第三场效应晶体管的漏极和第四场效应晶体管的漏极之间的第二电感器; 第三电感器，其磁耦合到所述第一电感器; 磁耦合到第二电感器的第四电感器; 第一电容器; 和第二电容器。
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公开(公告)号：US20110304387A1
公开(公告)日：2011-12-15
申请号：US13046953
申请日：2011-03-14
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs.
摘要翻译： 在一个实施例中，电流镜电路包括第一至第四绝缘栅场效应晶体管（FET）和偏置电路。 第一和第二FET的栅电极彼此连接。 第三FET的源电极连接到第一FET的漏电极，第三FET的漏电极连接到第一和第二FET的栅电极以及电流输入端。 第四FET的栅电极与第三FET的栅电极连接，第四FET的源电极与第二FET的漏极连接，第四FET的漏极成为电流输出端。 偏置电路被配置为向第三和第四FET的栅电极提供偏置电压。
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公开(公告)号：US08456227B2
公开(公告)日：2013-06-04
申请号：US13046953
申请日：2011-03-14
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs.
摘要翻译： 在一个实施例中，电流镜电路包括第一至第四绝缘栅场效应晶体管（FET）和偏置电路。 第一和第二FET的栅电极彼此连接。 第三FET的源电极连接到第一FET的漏电极，第三FET的漏电极连接到第一和第二FET的栅电极以及电流输入端。 第四FET的栅电极与第三FET的栅电极连接，第四FET的源电极与第二FET的漏极连接，第四FET的漏极成为电流输出端。 偏置电路被配置为向第三和第四FET的栅电极提供偏置电压。
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公开(公告)号：US20110234311A1
公开(公告)日：2011-09-29
申请号：US13047000
申请日：2011-03-14
申请人： Kenichi Hirashiki , Minoru Nagata
发明人： Kenichi Hirashiki , Minoru Nagata
IPC分类号： H03H11/00
CPC分类号： G01R19/0092
摘要： According to one embodiment, a current detection circuit is provided with: a NMOS transistor, whose control signal is given to a gate electrode, whose source electrode is connected to a ground line, and whose drain electrode is connected to an input/output terminal; a first PMOS transistor, in which the control signal is given to a gate electrode, and whose drain electrode is connected to the input/output terminal and the drain electrode of the NMOS transistor; and a second PMOS transistor, whose drain electrode is connected to the source electrode of the first PMOS transistor, and a first supply voltage is given to a source electrode. A detection section detects whether or not a current has changed at the input/output terminal from a change in current flowing through the second PMOS transistor.
摘要翻译： 根据一个实施例，电流检测电路具有：NMOS晶体管，其控制信号被提供给栅电极，源电极连接到接地线，其漏电极连接到输入/输出端; 第一PMOS晶体管，其中控制信号被提供给栅电极，并且其漏电极连接到NMOS晶体管的输入/输出端子和漏电极; 以及第二PMOS晶体管，其漏极连接到第一PMOS晶体管的源电极，并且向源电极提供第一电源电压。 检测部分检测在流过第二PMOS晶体管的电流的变化中电流是否在输入/输出端子处改变。
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