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14 条记录 (耗时 0.03 秒)

    Vertical vibration control device
    1.
    发明授权
    Vertical vibration control device 失效
    垂直振动控制装置

    公开(公告)号：US5327692A

    公开(公告)日：1994-07-12

    申请号：US922176

    申请日：1992-07-30

    申请人： Kenichi Yano ,  Hideo Hayashi ,  Ryuichi Kamimura ,  Masamitsu Miyamura ,  Jun Matsushima ,  Toru Kasai ,  Katsuhisa Kanda ,  Nobumitsu Funaki

    发明人： Kenichi Yano ,  Hideo Hayashi ,  Ryuichi Kamimura ,  Masamitsu Miyamura ,  Jun Matsushima ,  Toru Kasai ,  Katsuhisa Kanda ,  Nobumitsu Funaki

    IPC分类号： E04H9/02 ,  E02D27/34

    CPC分类号： E04H9/021 ,  E04H2009/026

    摘要： A device to control vertical vibration of a building caused by seismic disturbance. Air springs are positioned and secured between the building foundation and the building superstructure to attenuate vertical vibration of the building. Vertical support rails are secured to the foundation and/or to the building superstructure on opposite sides of, and adjacent to, the air springs. Horizontal connecting brackets are rigidly secured to the air springs and slidably secured to the adjacent rails. The brackets restrain horizontal deflection of the air springs without interfering with vertical reciprocation of the air springs.

    摘要翻译： 一种用于控制由地震干扰引起的建筑垂直振动的装置。 空气弹簧定位并固定在建筑基础和建筑物上部结构之间，以减弱建筑物的垂直振动。 垂直的支撑轨道固定到空气弹簧的相对侧和邻近的基础和/或建筑物上部结构。 水平连接支架刚性地固定在空气弹簧上并可滑动地固定在相邻的导轨上。 支架限制空气弹簧的水平偏转，而不会妨碍空气弹簧的垂直往复运动。

    Vertical vibration control device
    2.
    发明授权
    Vertical vibration control device 失效
    垂直振动控制装置

    公开(公告)号：US5433045A

    公开(公告)日：1995-07-18

    申请号：US215179

    申请日：1994-03-21

    申请人： Kenichi Yano ,  Hideo Hayashi ,  Ryuichi Kamimura ,  Masamitsu Miyamura ,  Jun Matsushima ,  Toru Kasai ,  Katsuhisa Kanda ,  Nobumitsu Funaki

    发明人： Kenichi Yano ,  Hideo Hayashi ,  Ryuichi Kamimura ,  Masamitsu Miyamura ,  Jun Matsushima ,  Toru Kasai ,  Katsuhisa Kanda ,  Nobumitsu Funaki

    IPC分类号： E04H9/02

    CPC分类号： E04H9/021 ,  E04H2009/026

    摘要： A device to control vertical vibration of a building caused by seismic disturbance. Air springs are positioned and secured between the building foundation and the building superstructure to attenuate vertical vibration of the building. Vertical support rails are secured to the foundation and/or to the building superstructure on opposite sides of, and adjacent to, the air springs. Horizontal connecting brackets are rigidly secured to the air springs and slidably secured to the adjacent rails. The brackets restrain horizontal deflection of the air springs without interfering with vertical reciprocation of the air springs.

    摘要翻译： 一种用于控制由地震干扰引起的建筑垂直振动的装置。 空气弹簧定位并固定在建筑基础和建筑物上部结构之间，以减弱建筑物的垂直振动。 垂直的支撑轨道固定到空气弹簧的相对侧和邻近的基础和/或建筑物上部结构。 水平连接支架刚性地固定在空气弹簧上并可滑动地固定在相邻的导轨上。 支架限制空气弹簧的水平偏转，而不会妨碍空气弹簧的垂直往复运动。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08037384B2

    公开(公告)日：2011-10-11

    申请号：US12340549

    申请日：2008-12-19

    申请人： Takumi Hasegawa ,  Motoyuki Sato ,  Tomoji Nakamura ,  Nobuo Konami ,  Jun Matsushima

    发明人： Takumi Hasegawa ,  Motoyuki Sato ,  Tomoji Nakamura ,  Nobuo Konami ,  Jun Matsushima

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318533

    摘要： A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing.

    摘要翻译： 半导体器件包括测试目标电路; 可扫描测试目标电路的扫描链; 形成提供给扫描链的测试图案的第一随机数生成电路; 与第一随机数生成电路分开设置的第二随机数生成电路; 以及使用由第二随机数生成电路产生的随机数来改变由第一随机数生成电路产生的随机数的随机数控制电路。 在半导体器件的测试中，由于扫描链的时钟周期不需要长于模式发生器的时钟周期，因此可以防止测试所需的模式发生器的时钟数 增加。 因此，可以防止测试时间增加。

    Test access control for plural processors of an integrated circuit
    4.
    发明授权
    Test access control for plural processors of an integrated circuit 有权
    集成电路的多个处理器的测试访问控制

    公开(公告)号：US07743278B2

    公开(公告)日：2010-06-22

    申请号：US11600208

    申请日：2006-11-16

    申请人： Yuri Ikeda ,  Yoshikazu Aoto ,  Jun Matsushima ,  Hiroyuki Sasaki ,  Tomoyoshi Ujii ,  Makoto Saen

    发明人： Yuri Ikeda ,  Yoshikazu Aoto ,  Jun Matsushima ,  Hiroyuki Sasaki ,  Tomoyoshi Ujii ,  Makoto Saen

    IPC分类号： G06F11/00

    CPC分类号： G01R31/31705 ,  G01R31/318572

    摘要： The present invention is directed to facilitate debugging in a semiconductor integrated circuit device including a plurality of microprocessors. A semiconductor integrated circuit device includes: a plurality of processors; a plurality of debug interfaces enabling debugging of the corresponding processors; a plurality of common terminals shared by the plurality of debug interfaces; a selection circuit capable of selectively connecting the plurality of debug interfaces to the common terminals; and a controller capable of controlling selecting operation in the selection circuit in accordance with a predetermined instruction. A first selector capable of selectively connecting the plurality of debug interfaces to a TRST terminal in the terminal group conformed with the JTAG specifications, and a second selector capable of selectively connecting the plurality of debug interfaces to terminals other than the TRST terminal are provided. With the configuration, even in the case where the number of processors increases, the invention can flexibly address the increase.

    摘要翻译： 本发明旨在促进包括多个微处理器的半导体集成电路器件的调试。 半导体集成电路装置包括：多个处理器; 多个调试接口，能够调试相应的处理器; 由所述多个调试接口共享的多个公共终端; 选择电路，其能够将所述多个调试接口选择性地连接到所述公共端子; 以及控制器，其能够根据预定指令来控制选择电路中的选择操作。 提供能够选择性地将多个调试接口连接到符合JTAG规范的终端组中的TRST终端的第一选择器，并且提供能够选择性地将多个调试接口连接到除了TRST终端之外的终端的第二选择器。 利用该配置，即使在处理器数量增加的情况下，本发明可以灵活地解决增加的问题。

    Image vibration reduction device
    7.
    发明授权
    Image vibration reduction device 失效
    图像减震装置

    公开(公告)号：US5696999A

    公开(公告)日：1997-12-09

    申请号：US712550

    申请日：1996-09-11

    申请人： Jun Matsushima ,  Tadashi Otani ,  Sueyuki Ohishi

    发明人： Jun Matsushima ,  Tadashi Otani ,  Sueyuki Ohishi

    IPC分类号： G02B27/64 ,  G03B5/00

    CPC分类号： G02B27/646 ,  G03B5/00 ,  G03B2205/0007 ,  G03B2217/005

    摘要： An image vibration reduction device for reducing an image vibration on an imaging surface includes a vibration reduction optical system movable to reduce the image vibration and constituting part of an imaging optical system, and a vibration reduction optical system displacement detector including a light-emission unit and a light-reception unit using an optical position detection element to optically detect a change in position of the vibration reduction optical system. The device also includes a light-emission amount automatic adjustment means for adjusting a light-emission amount of the light-emission unit at a predetermined time on the basis of an output from the light-reception unit.

    摘要翻译： 一种用于降低成像表面上的图像振动的图像减振装置包括可减少图像振动并构成成像光学系统的一部分的减振光学系统，以及包括发光单元和 光接收单元，其使用光学位置检测元件来光学地检测减振光学系统的位置变化。 该装置还包括发光量自动调节装置，用于根据光接收单元的输出在预定时间内调节发光单元的发光量。

    Apparatus and method for designing semiconductor device, and semiconductor device
    8.
    发明授权
    Apparatus and method for designing semiconductor device, and semiconductor device 有权
    用于设计半导体器件的设备和方法以及半导体器件

    公开(公告)号：US08887015B2

    公开(公告)日：2014-11-11

    申请号：US13544491

    申请日：2012-07-09

    申请人： Hiroyuki Iwata ,  Jun Matsushima

    发明人： Hiroyuki Iwata ,  Jun Matsushima

    IPC分类号： G01R31/28 ,  G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/14

    摘要： An arithmetic processor executes analysis processing for analyzing a probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state, and scan chain structure processing for structuring a scan chain for a plurality of scan flip-flop circuits having the same degree of probability that the output value after the capturing operation becomes the given logical state, on the basis of a result of the analyzing processing. The scan chain lower in a transition probability during the scan operation is formed so that a power consumption during a scan test can be reduced.

    摘要翻译： 算术处理器执行分析处理，用于分析在捕获操作之后扫描触发器电路的输出值变为给定逻辑状态的概率，以及用于构成用于多个扫描触发器电路的扫描链的扫描链结构处理 基于分析处理的结果，具有与拍摄操作之后的输出值成为给定逻辑状态的概率相同的程度。 在扫描操作期间以转换概率降低的扫描链形成为可以减少扫描测试期间的功耗。

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20090172488A1

    公开(公告)日：2009-07-02

    申请号：US12340549

    申请日：2008-12-19

    申请人： Takumi Hasegawa ,  Motoyuki Sato ,  Tomoji Nakamura ,  Nobuo Konami ,  Jun Matsushima

    发明人： Takumi Hasegawa ,  Motoyuki Sato ,  Tomoji Nakamura ,  Nobuo Konami ,  Jun Matsushima

    IPC分类号： G01R31/3187

    CPC分类号： G01R31/318533

    摘要： A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing.

    摘要翻译： 半导体器件包括测试目标电路; 可扫描测试目标电路的扫描链; 形成提供给扫描链的测试图案的第一随机数生成电路; 与第一随机数生成电路分开设置的第二随机数生成电路; 以及使用由第二随机数生成电路产生的随机数来改变由第一随机数生成电路产生的随机数的随机数控制电路。 在半导体器件的测试中，由于扫描链的时钟周期不需要长于模式发生器的时钟周期，因此可以防止测试所需的模式发生器的时钟数 增加。 因此，可以防止测试时间增加。

    Image blur compensation device with reduced noise effect mechanism
    10.
    发明授权
    Image blur compensation device with reduced noise effect mechanism 失效
    具有降低噪声影响机制的图像模糊补偿装置

    公开(公告)号：US06574436B2

    公开(公告)日：2003-06-03

    申请号：US08710108

    申请日：1996-09-12

    申请人： Tadashi Otani ,  Jun Matsushima

    发明人： Tadashi Otani ,  Jun Matsushima

    IPC分类号： G03B1700

    CPC分类号： H04N5/23258 ,  G03B2207/005 ,  G03B2217/005 ,  H04N5/23248 ,  H04N5/23287

    摘要： An image blur compensation device including a mechanism that can effectively reduce the effects of noise which becomes a problem in image blur compensation devices which are used in still cameras, video cameras, and the like. Particularly, the noise becomes a problem during position detection using a position sensitive device. The image blur compensation device includes an image blur compensation optical system to compensate for image blur arising due to blurring motion of an optical device, a position detection unit to detect the position of the image blur compensation optical system, an image blur compensation drive unit to drive the image blur compensation optical system based on the detection result of the position detection unit, and a power supply circuit which performs power supply to the position detection unit and the image blur compensation drive unit by a switching step-up control. The image blur compensation device includes an inhibition device to inhibit the detection operation of the position detection unit in a fixed period in which the switching phase of the power supply circuit has changed.

    摘要翻译： 一种图像模糊补偿装置，包括能够有效地减少在静止照相机，摄像机等中使用的图像模糊补偿装置中成为问题的噪声的影响的机构。 特别地，在使用位置敏感装置的位置检测中噪声成为问题。 图像模糊补偿装置包括：图像模糊补偿光学系统，用于补偿由于光学装置的模糊运动引起的图像模糊;检测图像模糊补偿光学系统的位置的位置检测单元;图像模糊补偿驱动单元， 基于位置检测单元的检测结果驱动图像模糊补偿光学系统;以及电源电路，其通过切换升压控制向位置检测单元和图像模糊补偿驱动单元供电。 图像模糊补偿装置包括禁止装置，其在电源电路的开关相位已经改变的固定时段中禁止位置检测单元的检测操作。