摘要:
According to one embodiment, an ultrasonic diagnostic apparatus comprises a data acquisition unit, an image generation unit, a calculation unit, a determination unit and a measurement unit. The data acquisition unit acquires a plurality of ultrasonic data. The image generation unit generates a plurality of ultrasonic images by using the plurality of ultrasonic data. The calculation unit calculates a feature amount for determining a shift between the two-dimensional section and a central axis of a target blood vessel. The determination unit determines an optimal image from the plurality of ultrasonic images based on the feature amount. The measurement unit measures an intima-media thickness of the target blood vessel by using the optimal image.
摘要:
According to one embodiment, an ultrasonic diagnosis apparatus includes a storage unit, a ultrasonic probe, a transmission/reception unit, a measured value calculation unit, a distance calculation unit, and a determination unit. The storage unit stores data of a state space based on a first measured values of a measurement item associated with an able-bodied person. The transmission/reception unit transmits ultrasonic waves to a subject via an ultrasonic probe, and generates reception signals corresponding to an ultrasonic waves reflected by the subject. The measured value calculation unit calculates a second measured value of the measurement item associated with the subject based on the reception signals. The distance calculation unit calculates a Mahalanobis distance of the subject based on the state space and the second measured value. The determination unit compares the Mahalanobis distance with a threshold to determine whether the subject has the disease evaluated by the measurement item.
摘要:
An ultrasound diagnostic apparatus according to an embodiment includes an extracting unit, a detecting unit, and a display controlling unit. The extracting unit extracts a cervical image region that is a region including the cervical region from an ultrasonic image of a fetus obtained by transmissions and receptions of ultrasonic waves. The detecting unit detects a dorsal body surface region that is a region that is related to a dorsal body surface of the fetus from the ultrasonic image. The display controlling unit controls to display an enlarged image including an enlarged image of the cervical image region in a region other than the dorsal region in the ultrasonic image on a display device.
摘要:
According to one embodiment, an ultrasonic diagnostic apparatus comprises a data acquisition unit, an image generation unit, a calculation unit, a determination unit and a measurement unit. The data acquisition unit acquires a plurality of ultrasonic data. The image generation unit generates a plurality of ultrasonic images by using the plurality of ultrasonic data. The calculation unit calculates a feature amount for determining a shift between the two-dimensional section and a central axis of a target blood vessel. The determination unit determines an optimal image from the plurality of ultrasonic images based on the feature amount. The measurement unit measures an intima-media thickness of the target blood vessel by using the optimal image.
摘要:
According to one embodiment, a ultrasonic diagnosis apparatus comprises an ultrasonic scanning unit configured to scan a region including at least part of a liver of an object with an ultrasonic wave and acquire an echo signal associated with the liver, an image generating unit configured to generate an ultrasonic image of the liver based on an echo signal associated with the liver, and a calculation unit configured to calculate at least one of a first index indicating an irregularity degree of the liver and a second index indicating an irregularity feature of the liver by using the ultrasonic image of the liver.
摘要:
The present invention provide a clock circuit and a method for providing a clock signal. The clock circuit includes: an adaptive clock generation circuit, configured to output an adaptive clock signal; and an adaptive clock driven circuit, configured to be driven by the adaptive clock signal to work. A maximum workable frequency of the adaptive clock driven circuit is higher than or equal to a frequency of the adaptive clock signal. When a working condition of the adaptive clock driven circuit is changed, the maximum workable frequency of the adaptive clock driven circuit is changed, the frequency of the adaptive clock signal which is output by the adaptive clock generation circuit is changed, and a changing direction of the frequency of an adaptive clock signal is consistent with that of the maximum workable frequency. The clock circuit and method may be used in design or manufacturing of a digital circuit.
摘要:
The present invention provide a clock circuit and a method for providing a clock signal. The clock circuit includes: an adaptive clock generation circuit, configured to output an adaptive clock signal; and an adaptive clock driven circuit, configured to be driven by the adaptive clock signal to work. A maximum workable frequency of the adaptive clock driven circuit is higher than or equal to a frequency of the adaptive clock signal. When a working condition of the adaptive clock driven circuit is changed, the maximum workable frequency of the adaptive clock driven circuit is changed, the frequency of the adaptive clock signal which is output by the adaptive clock generation circuit is changed, and a changing direction of the frequency of an adaptive clock signal is consistent with that of the maximum workable frequency. The clock circuit and method may be used in design or manufacturing of a digital circuit.
摘要:
A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication according to a dynamic frequency scaling (DFS) request signal sent by a bus side; blocking a current bus transfer according to the bus blocking indication; and feeding back a DFS response signal to the bus side after blocking the current bus transfer, where the DFS response signal is adapted to enable the bus side to perform a DFS operation. In the method, the bus transfer is temporarily blocked during the DFS, so that undesired influence on peripheral components caused by unstable bus block during the bus DFS is reduced without increasing the number of clock domains of the system or modifying the peripheral components, thus reducing the complexity of the implementation of the system, and improving the applicability of dynamic voltage frequency scaling (DVFS).
摘要:
The analysis image generating unit generates section images from volume analysis data that is collected by sending an ultrasound wave down to a region under the ribs. The right/left identifying unit identifies the right or left breast from cyclic motion components in the section images. The extending direction detecting unit analyzes plane-A images or plane-B images generated from the same volume analysis data, or a plane-C thickness-added MIP image, and detects the rib extending direction. The extending direction detecting unit also determines the position of the ultrasound probe based on the relative displacement of the extending direction. The body mark generating unit generates a body mark from the analysis results obtained by the right/left identifying unit and the extending direction detecting unit. The image synthesizing unit integrates the display image generated by the display image generating unit and the body mark, and displays it on the monitor.
摘要:
A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication according to a dynamic frequency scaling (DFS) request signal sent by a bus side; blocking a current bus transfer according to the bus blocking indication; and feeding back a DFS response signal to the bus side after blocking the current bus transfer, where the DFS response signal is adapted to enable the bus side to perform a DFS operation. In the method, the bus transfer is temporarily blocked during the DFS, so that undesired influence on peripheral components caused by unstable bus block during the bus DFS is reduced without increasing the number of clock domains of the system or modifying the peripheral components, thus reducing the complexity of the implementation of the system, and improving the applicability of dynamic voltage frequency scaling (DVFS).