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    Exposure mask and manufacturing method thereof
    2.
    发明授权
    Exposure mask and manufacturing method thereof 失效
    曝光掩模及其制造方法

    公开(公告)号：US5866280A

    公开(公告)日：1999-02-02

    申请号：US710408

    申请日：1996-09-17

    申请人： Shinichi Ito ,  Kenji Kawano ,  Soichi Inoue ,  Satoshi Tanaka

    发明人： Shinichi Ito ,  Kenji Kawano ,  Soichi Inoue ,  Satoshi Tanaka

    IPC分类号： G03F1/28 ,  G03F1/30 ,  G03F1/68 ,  G03F1/80 ,  H01L21/027 ,  G03F9/00

    CPC分类号： G03F1/26 ,  G03F1/30

    摘要： An exposure mask comprises a phase shift section including a plurality of opening patterns formed by making openings in part of a shading film provided on a transmissive substrate and digging part of the substrate, and a non-phase shift section including at least one opening pattern. The opening pattern of the non-phase shift section has a dig whose amount of digging has been adjusted according to the amount of digging in the opening patterns of the phase shift section.

    摘要翻译： 曝光掩模包括相移部分，其包括通过在设置在透射基板上的遮光膜的一部分上形成开口和挖掘基板的一部分而形成的多个开口图案，以及包括至少一个开口图案的非相移部分。 非相移部分的打开模式具有根据相移部分的打开模式中的挖掘量来调整挖掘量的挖掘。

    Light exposure mask
    6.
    发明授权
    Light exposure mask 失效
    曝光面膜

    公开(公告)号：US6030729A

    公开(公告)日：2000-02-29

    申请号：US79170

    申请日：1998-05-15

    申请人： Shinichi Ito ,  Kenji Kawano ,  Satoshi Tanaka

    发明人： Shinichi Ito ,  Kenji Kawano ,  Satoshi Tanaka

    IPC分类号： G03F1/30 ,  G03F1/68 ,  H01L21/027 ,  G03F9/00

    CPC分类号： G03F1/30 ,  G03F1/26

    摘要： Attention is paid to the shifting of a focal point depth due to an interference between some light penetrating even a light shielding film, that is, a light shielding film having a nonzero transmittance, and light passing through an opening. Study has been made about how both the transmittance of the light shielding film and the phase difference between the light penetrating the light shielding film and light passing through a light transmitting medium the same in thickness as the light shielding film vary, arriving at a conclusion that the broadest focal point tolerance can be obtained if a phase difference of substantially n.multidot..pi. (n: an positive integer) exists between light penetrating the light shielding film and light passing through the light transmitting medium.

    摘要翻译： 注意由于一些穿透即使是遮光膜的光，即具有非零透射率的遮光膜和穿过开口的光之间的干涉也导致焦点深度偏移。 已经研究了遮光膜的透射率以及透过遮光膜的光和穿过光透射介质的光的厚度与遮光膜的厚度相同的相位差是如何变化的，得出如下结论： 如果穿透遮光膜的光与通过光传输介质的光之间存在基本上nx pi（n：正整数）的相位差，则可以获得最宽的焦点公差。

    Method for making a design layout of a semiconductor integrated circuit
    7.
    再颁专利
    Method for making a design layout of a semiconductor integrated circuit 有权
    制造半导体集成电路的设计布局的方法

    公开(公告)号：USRE43659E1

    公开(公告)日：2012-09-11

    申请号：US12945672

    申请日：2010-11-12

    申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5081

    摘要： A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.

    摘要翻译： 提供了一种用于设计半导体集成电路的方法，其包括基于给定的设计规则压缩半导体集成电路的设计布局以获得压缩图案，预测在用于形成的晶片的表面区域形成的图案 所述半导体集成电路基于所述压实图案，通过将所述预测图案与所述压实图案进行比较来获得评价值，判定所述评价值是否满足预定条件，以及当所述评价值被判定为不满足时修改所述设计规则 预定条件。

    Semiconductor integrated circuit designing method and system using a design rule modification
    8.
    再颁专利
    Semiconductor integrated circuit designing method and system using a design rule modification 有权
    半导体集成电路设计方法和系统采用设计规则修改

    公开(公告)号：USRE42294E1

    公开(公告)日：2011-04-12

    申请号：US10819338

    申请日：2004-04-07

    申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22

    CPC分类号： G06F17/5081

    摘要： A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.

    摘要翻译： 提供了一种用于设计半导体集成电路的方法，其包括基于给定的设计规则压缩半导体集成电路的设计布局以获得压缩图案，预测在用于形成的晶片的表面区域形成的图案 所述半导体集成电路基于所述压实图案，通过将所述预测图案与所述压实图案进行比较来获得评价值，判定所述评价值是否满足预定条件，以及当所述评价值被判定为不满足时修改所述设计规则 预定条件。

    EVALUATION PATTERN GENERATING METHOD, COMPUTER PROGRAM PRODUCT, AND PATTERN VERIFYING METHOD
    9.
    发明申请
    EVALUATION PATTERN GENERATING METHOD, COMPUTER PROGRAM PRODUCT, AND PATTERN VERIFYING METHOD 审中-公开
    评估模式生成方法，计算机程序产品和模式验证方法

    公开(公告)号：US20100067777A1

    公开(公告)日：2010-03-18

    申请号：US12536900

    申请日：2009-08-06

    申请人： Katsuyoshi Kodera ,  Satoshi Tanaka ,  Shimon Maeda ,  Suigen Kyoh ,  Soichi Inoue ,  Ryuji Ogawa

    发明人： Katsuyoshi Kodera ,  Satoshi Tanaka ,  Shimon Maeda ,  Suigen Kyoh ,  Soichi Inoue ,  Ryuji Ogawa

    IPC分类号： G06K9/00

    CPC分类号： G03F1/44 ,  G03F1/36

    摘要： An evaluation pattern generating method including dividing a peripheral area of an evaluation target pattern into a plurality of meshes; calculating an image intensity of a circuit pattern when the evaluation target pattern is transferred onto a wafer by a lithography process in a case where a mask function value is given to a predetermined mesh; calculating a mask function value of the mesh so that a cost function of the image intensity, in which an optical image characteristic amount that affects a transfer performance of the evaluation target pattern to the wafer is set to the image intensity, satisfies a predetermined reference when evaluating a lithography performance of the evaluation target pattern; and generating an evaluation pattern corresponding to the mask function value.

    摘要翻译： 1.一种评价图案生成方法，包括将评价对象图案的周边区域划分为多个网格; 当将掩模函数值赋予预定网格时，通过光刻处理将评估对象图案转印到晶片上时，计算电路图案的图像强度; 计算网格的掩码函数值，使得影响评估对象图案对晶片的转印性能的光学图像特征量被设置为图像强度的图像强度的成本函数满足预定参考，当 评估目标模式的光刻性能评估; 以及生成与所述掩模功能值对应的评估图案。