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    Device for evaluating characteristic of insulated gate transistor
    1.
    发明授权
    Device for evaluating characteristic of insulated gate transistor 失效
    绝缘栅晶体管特性评估装置

    公开(公告)号：US06407573B1

    公开(公告)日：2002-06-18

    申请号：US09238887

    申请日：1999-01-28

    申请人： Kenji Yamaguchi ,  Hiroyuki Amishiro ,  Yuko Maruyama

    发明人： Kenji Yamaguchi ,  Hiroyuki Amishiro ,  Yuko Maruyama

    IPC分类号： G01R3126

    CPC分类号： G01R31/2621 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A transistor having a longer channel length and serving as a reference, and a transistor having a shorter channel length and to be subjected to effective channel length extraction are prepared (step ST1.1). A hypothetical point at which a change in a total drain-to-source resistance is estimated to be approximately zero when a gate overdrive is slightly changed is extracted in a mask channel length versus total drain-to-source resistance plane. The values of a function (F) are calculated which are defined by the difference between the rate of change in the total drain-to-source resistance and the product of a channel resistance per unit length and the rate of change in a mask channel length at the hypothetical points (step ST1.6). A true threshold voltage of the transistor having the shorter channel length is determined by a shift amount (&dgr;) which minimizes the standard deviation of the function (F) determined in the step ST1.7 (step ST1.10). A resistance-based method thus extracts an effective channel length and a series resistance with increased accuracy.

    摘要翻译： 制备具有较长沟道长度并用作基准的晶体管，以及具有较短沟道长度并经受有效沟道长度提取的晶体管（步骤ST1.1）。 当栅极过驱动略微改变时，估计总漏极 - 源极电阻的变化大致为零的假想点，掩模沟道长度对总漏极 - 源极电阻平面提取。 计算函数（F）的值，其由总漏极 - 源极电阻的变化率与每单位长度的沟道电阻的乘积与掩模沟道长度的变化率之间的差定义 在假想点（步骤ST1.6）。 具有较短信道长度的晶体管的真实阈值电压由步骤ST1.7中确定的函数（F）的标准偏差最小化的移位量（delta）确定（步骤ST1.10）。 因此，基于电阻的方法提高了精确度的有效通道长度和串联电阻。

    SWITCHING-DEVICE REMAINING LIFETIME DIAGNOSIS METHOD AND APPARATUS
    2.
    发明申请
    SWITCHING-DEVICE REMAINING LIFETIME DIAGNOSIS METHOD AND APPARATUS 有权
    切换设备剩余寿命诊断方法和设备

    公开(公告)号：US20120022797A1

    公开(公告)日：2012-01-26

    申请号：US13148817

    申请日：2009-02-23

    申请人： Akihiko Maruyama ,  Yuko Maruyama ,  Katsuhiko Horinouchi

    发明人： Akihiko Maruyama ,  Yuko Maruyama ,  Katsuhiko Horinouchi

    IPC分类号： G01B3/00

    CPC分类号： G05B23/0283 ,  G01R31/3274 ,  H01H3/001 ,  H01H33/6662 ,  H01H2071/044

    摘要： There are provided a switching-device remaining lifetime diagnosis method and a switching-device remaining lifetime diagnosis apparatus, wherein as status amount history data, there are accumulated status amounts related to a deterioration status of a switching device, estimated based on measurement data obtained through measurement of performance characteristics of the switching device; based on the accumulated status amount history data, there are created a plurality of system data pieces in which the status amounts are arranged with the respective abscissas of an elapsed time during an operation period of the switching device, the number of operations of the switching device, an inoperative time of the switching device, and an accumulated operation time of the switching device; based on the created system data pieces, the remaining lifetime of the switching device is estimated.

    摘要翻译： 提供了一种开关装置剩余寿命诊断方法和开关装置剩余寿命诊断装置，其中，作为状态量历史数据，存在与基于通过以下方式获得的测量数据估计的与开关装置的劣化状态相关的累积状态量 测量开关装置的性能特征; 基于累积状态量历史数据，创建多个系统数据，其中状态量在切换装置的操作周期期间以经过时间的横坐标排列，切换装置的操作次数 ，切换装置的不工作时间，以及开关装置的累计运行时间; 基于所创建的系统数据，估计开关装置的剩余寿命。

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110140277A1

    公开(公告)日：2011-06-16

    申请号：US13030861

    申请日：2011-02-18

    申请人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

    发明人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

    IPC分类号： H01L23/522

    CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

    摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07915708B2

    公开(公告)日：2011-03-29

    申请号：US12485528

    申请日：2009-06-16

    申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

    发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

    摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。