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公开(公告)号：US08699521B2
公开(公告)日：2014-04-15
申请号：US12986665
申请日：2011-01-07
IPC分类号： H04L1/00
CPC分类号： H04L67/02 , H04L49/90 , H04L49/9094 , H04L69/12
摘要： An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.
摘要翻译： 提供了一种用于在第一服务器中的主机存储器和网络适配器之间执行直接存储器访问（DMA）操作的装置。 该装置包括主机帧解析器和协议引擎。 主机帧解析器被配置为从主机接口接收对应于DMA操作的数据，并且被配置为以规定的间隔将动态的标记插入到数据中，并提供标记的数据，以便通过一个 网络结构。 协议引擎耦合到主机帧解析器。 协议引擎被配置为指导主机帧解析器插入标记，并且被配置为指定第一标记值和偏移值，由此使主机帧解析器能够定位并将第一标记插入到数据中。
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公开(公告)号：US20110099243A1
公开(公告)日：2011-04-28
申请号：US12986665
申请日：2011-01-07
IPC分类号： G06F15/167
CPC分类号： H04L67/02 , H04L49/90 , H04L49/9094 , H04L69/12
摘要： An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.
摘要翻译： 提供了一种用于在第一服务器中的主机存储器和网络适配器之间执行直接存储器访问（DMA）操作的装置。 该装置包括主机帧解析器和协议引擎。 主机帧解析器被配置为从主机接口接收对应于DMA操作的数据，并且被配置为以规定的间隔将动态的标记插入到数据中，并提供标记的数据，以便通过一个 网络结构。 协议引擎耦合到主机帧解析器。 协议引擎被配置为指导主机帧解析器插入标记，并且被配置为指定第一标记值和偏移值，由此使主机帧解析器能够定位并将第一标记插入到数据中。
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公开(公告)号：US20140164471A1
公开(公告)日：2014-06-12
申请号：US14183133
申请日：2014-02-18
IPC分类号： H04L29/08
CPC分类号： H04L67/02 , H04L49/90 , H04L49/9094 , H04L69/12
摘要： An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.
摘要翻译： 提供了一种用于在第一服务器中的主机存储器和网络适配器之间执行直接存储器访问（DMA）操作的装置。 该装置包括主机帧解析器和协议引擎。 主机帧解析器被配置为从主机接口接收对应于DMA操作的数据，并且被配置为以规定的间隔将动态的标记插入到数据中，并提供标记的数据，以便通过一个 网络结构。 协议引擎耦合到主机帧解析器。 协议引擎被配置为指导主机帧解析器插入标记，并且被配置为指定第一标记值和偏移值，由此使主机帧解析器能够定位并将第一标记插入到数据中。
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公开(公告)号：US07889762B2
公开(公告)日：2011-02-15
申请号：US11624849
申请日：2007-01-19
IPC分类号： H04J3/24
CPC分类号： H04L67/02 , H04L49/90 , H04L49/9094 , H04L69/12
摘要： An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.
摘要翻译： 提供了一种用于在第一服务器中的主机存储器和网络适配器之间执行直接存储器访问（DMA）操作的装置。 该装置包括主机帧解析器和协议引擎。 主机帧解析器被配置为从主机接口接收对应于DMA操作的数据，并且被配置为以规定的间隔将动态的标记插入到数据中，并提供标记的数据，以便通过一个 网络结构。 协议引擎耦合到主机帧解析器。 协议引擎被配置为指导主机帧解析器插入标记，并且被配置为指定第一标记值和偏移值，由此使主机帧解析器能够定位并将第一标记插入到数据中。
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5.发明申请METHODS, APPARATUS AND SYSTEMS FOR FACILITATING RDMA OPERATIONS WITH REDUCED DOORBELL RINGS 有权方法，装备和系统，用于减少DOORBELL环的RDMA操作公开(公告)号：US20140089444A1
公开(公告)日：2014-03-27
申请号：US13628771
申请日：2012-09-27
IPC分类号： G06F15/167
CPC分类号： G06F15/17331
摘要： Methods, apparatus and systems for reducing usage of Doorbell Rings in connection with RDMA operations. A portion of system memory is employed as a Memory-Mapped Input/Output (MMIO) address space configured to be accessed via a hardware networking device. A Send Queue (SQ) is stored in MMIO and is used to facilitate processing of Work Requests (WRs) that are written to SQ entries by software and read from the SQ via the hardware networking device. The software and logic in the hardware networking device employ pointers identifying locations in the SQ corresponding to a next write WR entry slot and last read WR entry slot that are implemented to enable WRs to be written to and read from the SQ during ongoing operations under which the SQ is not emptied such that doorbell rings to notify the hardware networking device that new WRs have been written to the SQ are not required.
摘要翻译： 与RDMA操作相关的减少门铃环使用的方法，装置和系统。 系统存储器的一部分被用作经配置以经由硬件网络设备访问的存储器映射输入/输出（MMIO）地址空间。 发送队列（SQ）存储在MMIO中，用于促进通过软件写入SQ条目并通过硬件网络设备从SQ读取的工作请求（WR）的处理。 硬件网络设备中的软件和逻辑采用标识SQ中相应于下一个写入WR入口时隙的位置的指针，以及最后读取的WR入口时隙，其被实现为使得在正在进行的操作期间将WR写入到SQ并从其读取， SQ不能清空，以致门铃振铃以通知硬件网络设备不会向SQ写入新的WR。
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公开(公告)号：US20130262614A1
公开(公告)日：2013-10-03
申请号：US13993697
申请日：2011-09-29
IPC分类号： G06F15/173 , G06F5/14
CPC分类号： G06F15/17331 , G06F5/14 , G06F9/544
摘要： An embodiment may include circuitry that may write a message from a system memory in a host to a memory space in an input/output (I/O) controller in the host. A host operating system may reside, at least in part, in the system memory. The message may include both data and at least one descriptor associated with the data. The data may be included in the at least one descriptor. The circuitry also may signal the I/O controller that the writing has occurred. Many alternatives, variations, and modifications are possible.
摘要翻译： 实施例可以包括可以将消息从主机中的系统存储器写入主机中的输入/输出（I / O）控制器中的存储器空间的电路。 主机操作系统可以至少部分地驻留在系统存储器中。 消息可以包括数据和与数据相关联的至少一个描述符。 数据可以包括在至少一个描述符中。 该电路还可以向I / O控制器发出写入发生的信号。 许多替代方案，变化和修改是可能的。
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公开(公告)号：US08078743B2
公开(公告)日：2011-12-13
申请号：US11356493
申请日：2006-02-17
IPC分类号： G06F15/16
CPC分类号： H04L67/1097
摘要： A computer system such as a server pipelines RNIC interface (RI) management/control operations such as memory registration operations to hide from network applications the latency in performing RDMA work requests caused in part by delays in processing the memory registration operations and the time required to execute the registration operations themselves. A separate QP-like structure, called a control QP (CQP), interfaces with a control processor (CP) to form a control path pipeline, separate from the transaction pipeline, which is designated to handle all control path traffic associated with the processing of RI control operations. This includes memory registration operations (MR OPs), as well as the creation and destruction of traditional QPs for processing RDMA transactions. Once the MR OP has been queued in the control path pipeline of the adapter, a pending bit is set which is associated with the MR OP. Processing of an RDMA work request in the transaction pipeline that has engendered the enqueued MR OP is permitted to proceed as if the processing of the MR OP has already been completed. If the work request gets ahead of the MR OP, the associated pending bit being set will notify the adapter's work request transaction pipeline to stall (and possibly reschedule) completion of the work request until the processing of the MR OP for that memory region is complete. When the memory registration process for the memory region is complete, the associated pending bit is reset and the adapter transaction pipeline is permitted to continue processing the work request using the newly registered memory region.
摘要翻译： 计算机系统，例如服务器管线RNIC接口（RI）管理/控制操作，诸如存储器注册操作，以从网络应用中隐藏执行RDMA工作请求的延迟部分地由于处理存储器注册操作的延迟和所需的时间 执行注册操作本身。 称为控制QP（CQP）的独立QP类结构与控制处理器（CP）接口，以形成与事务流水线分开的控制路径流水线，其被指定为处理与处理相关联的所有控制路径流量 RI控制操作。 这包括内存注册操作（MR OP），以及创建和销毁用于处理RDMA事务的传统QP。 一旦MR OP已经在适配器的控制路径管道中排队，则设置与MR OP相关联的挂起位。 如果已经完成了MR操作的处理，处理已经引入入站的MR OP的事务流水线中的RDMA工作请求被执行。 如果工作请求超过MR OP，则相关的待处理位将被设置将通知适配器的工作请求事务流水线停止（可能重新计划）工作请求的完成，直到该存储器区域的MR OP的处理完成 。 当存储器区域的存储器注册过程完成时，相关联的挂起位被复位，并且适配器事务流水线被允许使用新登记的存储器区域继续处理工作请求。
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公开(公告)号：US09405725B2
公开(公告)日：2016-08-02
申请号：US13993697
申请日：2011-09-29
IPC分类号： G06F15/167 , G06F15/173 , G06F5/14 , G06F9/54
CPC分类号： G06F15/17331 , G06F5/14 , G06F9/544
摘要： An embodiment may include circuitry that may write a message from a system memory in a host to a memory space in an input/output (I/O) controller in the host. A host operating system may reside, at least in part, in the system memory. The message may include both data and at least one descriptor associated with the data. The data may be included in the at least one descriptor. The circuitry also may signal the I/O controller that the writing has occurred.
摘要翻译： 实施例可以包括可以将消息从主机中的系统存储器写入主机中的输入/输出（I / O）控制器中的存储器空间的电路。 主机操作系统可以至少部分地驻留在系统存储器中。 消息可以包括数据和与数据相关联的至少一个描述符。 数据可以包括在至少一个描述符中。 该电路还可以向I / O控制器发出写入发生的信号。
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9.发明授权Apparatus and method for packet transmission over a high speed network supporting remote direct memory access operations 有权用于支持远程直接存储器访问操作的高速网络上的分组传输的装置和方法公开(公告)号：US08458280B2
公开(公告)日：2013-06-04
申请号：US11315685
申请日：2005-12-22
IPC分类号： G06F15/167
CPC分类号： H04L67/1097 , H04L47/6265
摘要： A mechanism for performing remote direct memory access (RDMA) operations between a first server and a second server over an Ethernet fabric. The RDMA operations are initiated by execution of a verb according to a remote direct memory access protocol. The verb is executed by a CPU on the first server. The apparatus includes transaction logic that is configured to process a work queue element corresponding to the verb, and that is configured to accomplish the RDMA operations over a TCP/IP interface between the first and second servers, where the work queue element resides within first host memory corresponding to the first server. The transaction logic includes transmit history information stores and a protocol engine. The transmit history information stores maintains parameters associated with said work queue element. The protocol engine is coupled to the transmit history information stores and is configured to access the parameters to enable retransmission of one or more TCP segments corresponding to the RDMA operations.
摘要翻译： 用于通过以太网结构在第一服务器和第二服务器之间执行远程直接存储器访问（RDMA）操作的机制。 根据远程直接存储器访问协议执行动词来启动RDMA操作。 动词由第一台服务器上的CPU执行。 该装置包括被配置为处理与该动词对应的工作队列元素的事务逻辑，并且被配置为通过第一和第二服务器之间的TCP / IP接口完成RDMA操作，其中工作队列元素驻留在第一主机 内存对应于第一台服务器。 交易逻辑包括发送历史信息存储和协议引擎。 发送历史信息存储维护与所述工作队列元素相关联的参数。 协议引擎被耦合到发送历史信息存储，并且被配置为访问参数以使得能够重传与RDMA操作相对应的一个或多个TCP段。
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10.发明申请METHOD AND APPARATUS FOR USING A SINGLE MULTI-FUNCTION ADAPTER WITH DIFFERENT OPERATING SYSTEMS 有权使用具有不同操作系统的单个多功能适配器的方法和装置公开(公告)号：US20100332694A1
公开(公告)日：2010-12-30
申请号：US12874739
申请日：2010-09-02
CPC分类号： G06F13/385
摘要： A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface.
摘要翻译： 灵活的布置允许根据需要单独布置以太网通道适配器（ECA）硬件功能，以符合各种操作系统部署模型。 PCI接口提供适合于相关操作系统的虚拟设备的逻辑模型。 映射参数和值与分组流相关联，以允许根据所提出的逻辑模型和所需的操作来适当地处理分组流。 映射发生在主机端和网络侧，以允许执行ECA的多个操作，同时仍允许在每个接口处正确传送。
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