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公开(公告)号：US08699521B2
公开(公告)日：2014-04-15
申请号：US12986665
申请日：2011-01-07
IPC分类号： H04L1/00
CPC分类号： H04L67/02 , H04L49/90 , H04L49/9094 , H04L69/12
摘要： An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.
摘要翻译： 提供了一种用于在第一服务器中的主机存储器和网络适配器之间执行直接存储器访问（DMA）操作的装置。 该装置包括主机帧解析器和协议引擎。 主机帧解析器被配置为从主机接口接收对应于DMA操作的数据，并且被配置为以规定的间隔将动态的标记插入到数据中，并提供标记的数据，以便通过一个 网络结构。 协议引擎耦合到主机帧解析器。 协议引擎被配置为指导主机帧解析器插入标记，并且被配置为指定第一标记值和偏移值，由此使主机帧解析器能够定位并将第一标记插入到数据中。
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2.发明申请METHODS, APPARATUS AND SYSTEMS FOR FACILITATING RDMA OPERATIONS WITH REDUCED DOORBELL RINGS 有权方法，装备和系统，用于减少DOORBELL环的RDMA操作公开(公告)号：US20140089444A1
公开(公告)日：2014-03-27
申请号：US13628771
申请日：2012-09-27
IPC分类号： G06F15/167
CPC分类号： G06F15/17331
摘要： Methods, apparatus and systems for reducing usage of Doorbell Rings in connection with RDMA operations. A portion of system memory is employed as a Memory-Mapped Input/Output (MMIO) address space configured to be accessed via a hardware networking device. A Send Queue (SQ) is stored in MMIO and is used to facilitate processing of Work Requests (WRs) that are written to SQ entries by software and read from the SQ via the hardware networking device. The software and logic in the hardware networking device employ pointers identifying locations in the SQ corresponding to a next write WR entry slot and last read WR entry slot that are implemented to enable WRs to be written to and read from the SQ during ongoing operations under which the SQ is not emptied such that doorbell rings to notify the hardware networking device that new WRs have been written to the SQ are not required.
摘要翻译： 与RDMA操作相关的减少门铃环使用的方法，装置和系统。 系统存储器的一部分被用作经配置以经由硬件网络设备访问的存储器映射输入/输出（MMIO）地址空间。 发送队列（SQ）存储在MMIO中，用于促进通过软件写入SQ条目并通过硬件网络设备从SQ读取的工作请求（WR）的处理。 硬件网络设备中的软件和逻辑采用标识SQ中相应于下一个写入WR入口时隙的位置的指针，以及最后读取的WR入口时隙，其被实现为使得在正在进行的操作期间将WR写入到SQ并从其读取， SQ不能清空，以致门铃振铃以通知硬件网络设备不会向SQ写入新的WR。
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公开(公告)号：US20110099243A1
公开(公告)日：2011-04-28
申请号：US12986665
申请日：2011-01-07
IPC分类号： G06F15/167
CPC分类号： H04L67/02 , H04L49/90 , H04L49/9094 , H04L69/12
摘要： An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.
摘要翻译： 提供了一种用于在第一服务器中的主机存储器和网络适配器之间执行直接存储器访问（DMA）操作的装置。 该装置包括主机帧解析器和协议引擎。 主机帧解析器被配置为从主机接口接收对应于DMA操作的数据，并且被配置为以规定的间隔将动态的标记插入到数据中，并提供标记的数据，以便通过一个 网络结构。 协议引擎耦合到主机帧解析器。 协议引擎被配置为指导主机帧解析器插入标记，并且被配置为指定第一标记值和偏移值，由此使主机帧解析器能够定位并将第一标记插入到数据中。
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4.发明授权
公开(公告)号：US6148359A
公开(公告)日：2000-11-14
申请号：US186597
申请日：1998-11-05
CPC分类号： G06F13/4027 , G06F13/4059
摘要： A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-EISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches the bridge interface from the bridge or PCI bus, and it is recognized that the address is within the range, then the fast burst mode is allowed, and write addresses are allowed to follow one another without the delay for the snoop phase or the possibility of defer or retry.
摘要翻译： 计算机系统在微处理器本身的控制下具有处理器总线，并且该总线与主存储器通信，为大多数缓存填充操作提供高性能访问。 此外，该系统包括一个或多个扩展总线，优选地在示例性实施例中为PCI类型。 主机到PCI桥接器用于将处理器总线耦合到扩展总线。 例如，其他总线可以通过PCI-to-EISA桥耦合到PCI总线。 主机到PCI桥接器包含发布的写入和延迟读取请求的队列。 所有交易排队通过桥梁，上游或下游。 系统总线是超级管道，因为交易重叠。 在桥接器和主存储器之间允许快速突发事务，即，可以在不延迟或重试的情况下满足的请求被应用于系统总线，而不等待从目标获得响应。 地址范围（例如，系统存储器地址）被定义为快速突发范围，并且该范围内的任何地址与该范围之外的地址不同。 通过配置周期对桥进行编程，以建立此快速突发范围，在此范围内，已知无法接收到无序响应。 当事务从桥接器或PCI总线到达桥接口时，并且认识到地址在该范围内，则允许快速突发模式，并且允许写入地址彼此跟随，而没有窥探阶段的延迟 或延迟或重试的可能性。
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公开(公告)号：US20130262614A1
公开(公告)日：2013-10-03
申请号：US13993697
申请日：2011-09-29
IPC分类号： G06F15/173 , G06F5/14
CPC分类号： G06F15/17331 , G06F5/14 , G06F9/544
摘要： An embodiment may include circuitry that may write a message from a system memory in a host to a memory space in an input/output (I/O) controller in the host. A host operating system may reside, at least in part, in the system memory. The message may include both data and at least one descriptor associated with the data. The data may be included in the at least one descriptor. The circuitry also may signal the I/O controller that the writing has occurred. Many alternatives, variations, and modifications are possible.
摘要翻译： 实施例可以包括可以将消息从主机中的系统存储器写入主机中的输入/输出（I / O）控制器中的存储器空间的电路。 主机操作系统可以至少部分地驻留在系统存储器中。 消息可以包括数据和与数据相关联的至少一个描述符。 数据可以包括在至少一个描述符中。 该电路还可以向I / O控制器发出写入发生的信号。 许多替代方案，变化和修改是可能的。
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公开(公告)号：US08078743B2
公开(公告)日：2011-12-13
申请号：US11356493
申请日：2006-02-17
IPC分类号： G06F15/16
CPC分类号： H04L67/1097
摘要： A computer system such as a server pipelines RNIC interface (RI) management/control operations such as memory registration operations to hide from network applications the latency in performing RDMA work requests caused in part by delays in processing the memory registration operations and the time required to execute the registration operations themselves. A separate QP-like structure, called a control QP (CQP), interfaces with a control processor (CP) to form a control path pipeline, separate from the transaction pipeline, which is designated to handle all control path traffic associated with the processing of RI control operations. This includes memory registration operations (MR OPs), as well as the creation and destruction of traditional QPs for processing RDMA transactions. Once the MR OP has been queued in the control path pipeline of the adapter, a pending bit is set which is associated with the MR OP. Processing of an RDMA work request in the transaction pipeline that has engendered the enqueued MR OP is permitted to proceed as if the processing of the MR OP has already been completed. If the work request gets ahead of the MR OP, the associated pending bit being set will notify the adapter's work request transaction pipeline to stall (and possibly reschedule) completion of the work request until the processing of the MR OP for that memory region is complete. When the memory registration process for the memory region is complete, the associated pending bit is reset and the adapter transaction pipeline is permitted to continue processing the work request using the newly registered memory region.
摘要翻译： 计算机系统，例如服务器管线RNIC接口（RI）管理/控制操作，诸如存储器注册操作，以从网络应用中隐藏执行RDMA工作请求的延迟部分地由于处理存储器注册操作的延迟和所需的时间 执行注册操作本身。 称为控制QP（CQP）的独立QP类结构与控制处理器（CP）接口，以形成与事务流水线分开的控制路径流水线，其被指定为处理与处理相关联的所有控制路径流量 RI控制操作。 这包括内存注册操作（MR OP），以及创建和销毁用于处理RDMA事务的传统QP。 一旦MR OP已经在适配器的控制路径管道中排队，则设置与MR OP相关联的挂起位。 如果已经完成了MR操作的处理，处理已经引入入站的MR OP的事务流水线中的RDMA工作请求被执行。 如果工作请求超过MR OP，则相关的待处理位将被设置将通知适配器的工作请求事务流水线停止（可能重新计划）工作请求的完成，直到该存储器区域的MR OP的处理完成 。 当存储器区域的存储器注册过程完成时，相关联的挂起位被复位，并且适配器事务流水线被允许使用新登记的存储器区域继续处理工作请求。
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7.发明授权Lock protocol for PCI bus using an additional "superlock" signal on the system bus 失效使用系统总线上附加“超级锁”信号的PCI总线锁定协议
公开(公告)号：US6098134A
公开(公告)日：2000-08-01
申请号：US775130
申请日：1996-12-31
CPC分类号： G06F9/52
摘要： A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E)ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available. A contemporary microprocessor such as a P6 has a deferred transaction protocol to implement split transactions, but this protocol is not available on a PCI bus. Split transactions are done by a "retry" command on a PCI bus, wherein a read request that cannot be completed immediately is queued and a "retry" response is sent back to the requester on the bus; this instructs the requester to retry (send the same command again) at a later time. To avoid a situation where two processors issue locked cycles which are enqueued and retried in separate bridges, a "Superlock" signal is added to the processor bus, which is asserted by a bridge as soon as a locked transaction is enqueued, and thereafter neither bridge will accept a locked cycle issued by a processor, other than that locked read that was initiated by a processor and enqueued in the bridge and is being retried.
摘要翻译： 计算机系统在微处理器本身的控制下具有处理器总线，并且该总线与主存储器通信，为大多数缓存填充操作提供高性能访问。 此外，该系统包括一个或多个扩展总线，优选地在示例性实施例中为PCI类型。 主机到PCI桥接器用于将处理器总线耦合到扩展总线。 例如，其他总线可以通过PCI至（E）ISA网桥耦合到PCI总线。 主机到PCI桥接器包含发布的写入和延迟读取请求的队列。 所有交易排队通过桥梁，上游或下游。 根据本发明的特征，提供分割事务，即，在请求它的处理器仍然在总线上时不满足的读请求，而是在读取结果为止之前放弃总线并且其他事务干预 可用。 诸如P6的当代微处理器具有延迟事务协议来实现分离事务，但是该协议在PCI总线上不可用。 拆分事务通过PCI总线上的“重试”命令完成，其中立即不能完成的读取请求被排队，并且“重试”响应被发送回总线上的请求者; 这指示请求者稍后重试（再次发送相同的命令）。 为了避免两个处理器发出锁定循环的情况，这些循环在单独的桥接器中排队并重试，“Superlock”信号被添加到处理器总线中，一旦锁定的事务被入队就由桥接器断言，然后两个桥接器 将接受处理器发出的锁定循环，而不是由处理器启动并处于桥中并正在重试的锁定读取。
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公开(公告)号：US6070209A
公开(公告)日：2000-05-30
申请号：US196373
申请日：1998-11-19
申请人： Brian S. Hausauer
发明人： Brian S. Hausauer
CPC分类号： G06F13/4059
摘要： A bridge device for delivering data transactions between devices on two data buses in a computer system includes, for each pair of devices that may transact across the bridge device, a dedicated storage area that aids in completing transactions between the devices in the pair. The bridge device also includes a controller that allows transactions in one dedicated storage area to be completed without regard to the completion of earlier-issued transactions in another dedicated storage area.
摘要翻译： 用于在计算机系统中的两个数据总线上的设备之间递送数据事务的桥接设备包括用于跨越桥接设备交互的每对设备，辅助完成该对中的设备之间的事务的专用存储区域。 桥接设备还包括控制器，其允许在一个专用存储区域中的事务完成，而不考虑在另一专用存储区域中完成先前发布的事务。
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公开(公告)号：US09405725B2
公开(公告)日：2016-08-02
申请号：US13993697
申请日：2011-09-29
IPC分类号： G06F15/167 , G06F15/173 , G06F5/14 , G06F9/54
CPC分类号： G06F15/17331 , G06F5/14 , G06F9/544
摘要： An embodiment may include circuitry that may write a message from a system memory in a host to a memory space in an input/output (I/O) controller in the host. A host operating system may reside, at least in part, in the system memory. The message may include both data and at least one descriptor associated with the data. The data may be included in the at least one descriptor. The circuitry also may signal the I/O controller that the writing has occurred.
摘要翻译： 实施例可以包括可以将消息从主机中的系统存储器写入主机中的输入/输出（I / O）控制器中的存储器空间的电路。 主机操作系统可以至少部分地驻留在系统存储器中。 消息可以包括数据和与数据相关联的至少一个描述符。 数据可以包括在至少一个描述符中。 该电路还可以向I / O控制器发出写入发生的信号。
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10.发明授权Apparatus and method for packet transmission over a high speed network supporting remote direct memory access operations 有权用于支持远程直接存储器访问操作的高速网络上的分组传输的装置和方法公开(公告)号：US08458280B2
公开(公告)日：2013-06-04
申请号：US11315685
申请日：2005-12-22
IPC分类号： G06F15/167
CPC分类号： H04L67/1097 , H04L47/6265
摘要： A mechanism for performing remote direct memory access (RDMA) operations between a first server and a second server over an Ethernet fabric. The RDMA operations are initiated by execution of a verb according to a remote direct memory access protocol. The verb is executed by a CPU on the first server. The apparatus includes transaction logic that is configured to process a work queue element corresponding to the verb, and that is configured to accomplish the RDMA operations over a TCP/IP interface between the first and second servers, where the work queue element resides within first host memory corresponding to the first server. The transaction logic includes transmit history information stores and a protocol engine. The transmit history information stores maintains parameters associated with said work queue element. The protocol engine is coupled to the transmit history information stores and is configured to access the parameters to enable retransmission of one or more TCP segments corresponding to the RDMA operations.
摘要翻译： 用于通过以太网结构在第一服务器和第二服务器之间执行远程直接存储器访问（RDMA）操作的机制。 根据远程直接存储器访问协议执行动词来启动RDMA操作。 动词由第一台服务器上的CPU执行。 该装置包括被配置为处理与该动词对应的工作队列元素的事务逻辑，并且被配置为通过第一和第二服务器之间的TCP / IP接口完成RDMA操作，其中工作队列元素驻留在第一主机 内存对应于第一台服务器。 交易逻辑包括发送历史信息存储和协议引擎。 发送历史信息存储维护与所述工作队列元素相关联的参数。 协议引擎被耦合到发送历史信息存储，并且被配置为访问参数以使得能够重传与RDMA操作相对应的一个或多个TCP段。
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