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公开(公告)号：US20080316852A1
公开(公告)日：2008-12-25
申请号：US12140071
申请日：2008-06-16
CPC分类号： G11C17/18 , G11C17/16 , H01L27/112 , H01L27/11206
摘要： A nonvolatile semiconductor memory device comprises an array of memory cells each including an antifuse to store information based on a variation in resistance in accordance with destruction of the insulator in the antifuse. The antifuse includes a semiconductor substrate, a first conduction layer formed in the surface of the semiconductor substrate, a first electrode provided on the first conduction layer to be given a first voltage, a second conduction layer provided on the semiconductor substrate with the insulator interposed therebetween, and a second electrode provided on the second conduction layer to be given a second voltage different from the first voltage. The first electrode or the second electrode is formed of a metal silicide.
摘要翻译： 非易失性半导体存储器件包括存储单元阵列，每个存储单元包括反熔丝，以根据抗反熔丝中的绝缘体的破坏来存储基于电阻变化的信息。 反熔丝包括半导体衬底，形成在半导体衬底的表面中的第一导电层，设置在第一导电层上以被赋予第一电压的第一电极，设置在半导体衬底上的绝缘体之间的第二导电层 以及设置在所述第二导电层上的第二电极，以被赋予不同于所述第一电压的第二电压。 第一电极或第二电极由金属硅化物形成。
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公开(公告)号：US07796460B2
公开(公告)日：2010-09-14
申请号：US12140071
申请日：2008-06-16
IPC分类号： G11C8/00
CPC分类号： G11C17/18 , G11C17/16 , H01L27/112 , H01L27/11206
摘要： A nonvolatile semiconductor memory device comprises an array of memory cells each including an antifuse to store information based on a variation in resistance in accordance with destruction of the insulator in the antifuse. The antifuse includes a semiconductor substrate, a first conduction layer formed in the surface of the semiconductor substrate, a first electrode provided on the first conduction layer to be given a first voltage, a second conduction layer provided on the semiconductor substrate with the insulator interposed therebetween, and a second electrode provided on the second conduction layer to be given a second voltage different from the first voltage. The first electrode or the second electrode is formed of a metal silicide.
摘要翻译： 非易失性半导体存储器件包括存储单元阵列，每个存储单元包括反熔丝，以根据抗反熔丝中的绝缘体的破坏来存储基于电阻变化的信息。 反熔丝包括半导体衬底，形成在半导体衬底的表面中的第一导电层，设置在第一导电层上以被赋予第一电压的第一电极，设置在半导体衬底上的绝缘体之间的第二导电层 以及设置在所述第二导电层上的第二电极，以被赋予不同于所述第一电压的第二电压。 第一电极或第二电极由金属硅化物形成。
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公开(公告)号：US20100182819A1
公开(公告)日：2010-07-22
申请号：US12690623
申请日：2010-01-20
摘要： A nonvolatile semiconductor memory device comprising: a memory cell array in which two bit lines are provided to each one bit of input data, and memory cells each including an anti-fuse element are arranged at an intersection point between one of the two bit lines and an even address word line, and an intersection point between the other one of the two bit lines and an odd address word line, respectively; a plurality of booster circuits which are arranged in a plurality of memory banks, respectively, and each of which generates a write voltage and a read voltage to be supplied to a corresponding one of the anti-fuse elements of the respective memory banks, each of the memory banks obtained by dividing the memory cell array; a booster circuit controller to issue an instruction to generate the write voltage and the read voltage to the plurality of booster circuits; a word line selector to activate a different word line at the time of writing from one to be activated at the time of reading, with respect to the same address value of an address signal; a write bit line selector to select bit lines one by one from the memory banks, respectively, at the time of writing, the bit lines performing writing simultaneously; and a read bit line selector to select a bit line at the time of reading, the bit line outputting data.
摘要翻译： 一种非易失性半导体存储器件，包括：存储单元阵列，其中向每一位输入数据提供两个位线，并且每个包括反熔丝元件的存储单元布置在两个位线之一和 偶数地址字线和两条位线中的另一条位线和奇数地址字线之间的交点; 分别布置在多个存储体中的多个升压电路，并且每个升压电路产生写入电压和读取电压以供应给相应存储体的相应的一个反熔丝元件， 通过划分存储单元阵列获得的存储体; 升压电路控制器，向多个升压电路发出产生写入电压和读取电压的指令; 相对于地址信号的相同地址值，字线选择器在写入时激活不同字线，以便在读取时被激活; 写位线选择器，分别在写入时从存储体中逐个地选择位线，位线同时执行写入; 和读位线选择器，用于在读取时选择位线，位线输出数据。
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公开(公告)号：US08120974B2
公开(公告)日：2012-02-21
申请号：US12690623
申请日：2010-01-20
IPC分类号： G11C7/00
摘要： A nonvolatile semiconductor memory device comprising: a memory cell array in which two bit lines are provided to each one bit of input data, and memory cells each including an anti-fuse element are arranged at an intersection point between one of the two bit lines and an even address word line, and an intersection point between the other one of the two bit lines and an odd address word line, respectively; a plurality of booster circuits which are arranged in a plurality of memory banks, respectively, and each of which generates a write voltage and a read voltage to be supplied to a corresponding one of the anti-fuse elements of the respective memory banks, each of the memory banks obtained by dividing the memory cell array; a booster circuit controller to issue an instruction to generate the write voltage and the read voltage to the plurality of booster circuits; a word line selector to activate a different word line at the time of writing from one to be activated at the time of reading, with respect to the same address value of an address signal; a write bit line selector to select bit lines one by one from the memory banks, respectively, at the time of writing, the bit lines performing writing simultaneously; and a read bit line selector to select a bit line at the time of reading, the bit line outputting data.
摘要翻译： 一种非易失性半导体存储器件，包括：存储单元阵列，其中向每一位输入数据提供两个位线，并且每个包括反熔丝元件的存储单元布置在两个位线之一和 偶数地址字线和两条位线中的另一条位线和奇数地址字线之间的交点; 分别布置在多个存储体中的多个升压电路，并且每个升压电路产生写入电压和读取电压以供应给相应存储体的相应的一个反熔丝元件， 通过划分存储单元阵列获得的存储体; 升压电路控制器，向多个升压电路发出产生写入电压和读取电压的指令; 相对于地址信号的相同地址值，字线选择器在写入时激活不同字线，以便在读取时被激活; 写位线选择器，分别在写入时从存储体中逐个地选择位线，位线同时执行写入; 和读位线选择器，用于在读取时选择位线，位线输出数据。
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公开(公告)号：US07630226B2
公开(公告)日：2009-12-08
申请号：US11971425
申请日：2008-01-09
IPC分类号： G11C17/00
摘要： A memory cell includes: an irreversible storage element that writes data by breaking down an insulating film, with a write voltage being applied to its one end; and first and second transistors with one end being connected to the other end of the irreversible storage element. A non-volatile semiconductor storage device includes: the memory cell; write word lines and read word lines that are connected to the first transistor and the second transistor, respectively; write bit lines and read bit lines that are connected to the first transistor and the other end of the second transistor, respectively; a row decoder selectively driving the write word lines and the read word lines; and a write-disturb prevention circuit charging the read bit lines to a certain voltage in writing data.
摘要翻译： 存储单元包括：不可逆存储元件，其通过分解绝缘膜来写入数据，其中写入电压被施加到其一端; 以及第一和第二晶体管，其一端连接到不可逆存储元件的另一端。 非易失性半导体存储装置包括：存储单元; 分别写入连接到第一晶体管和第二晶体管的字线和读字线; 分别写入连接到第一晶体管和第二晶体管的另一端的位线和读位线; 行解码器选择性地驱动写字线和读字线; 以及在写入数据时将读取位线充电到一定电压的写入干扰防止电路。
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公开(公告)号：US20080165586A1
公开(公告)日：2008-07-10
申请号：US11971425
申请日：2008-01-09
IPC分类号： G11C16/06
摘要： A memory cell includes: an irreversible storage element that writes data by breaking down an insulating film, with a write voltage being applied to its one end; and first and second transistors with one end being connected to the other end of the irreversible storage element. A non-volatile semiconductor storage device includes: the memory cell; write word lines and read word lines that are connected to the first transistor and the second transistor, respectively; write bit lines and read bit lines that are connected to the first transistor and the other end of the second transistor, respectively; a row decoder selectively driving the write word lines and the read word lines; and a write-disturb prevention circuit charging the read bit lines to a certain voltage in writing data.
摘要翻译： 存储单元包括：不可逆存储元件，其通过分解绝缘膜来写入数据，其中写入电压被施加到其一端; 以及第一和第二晶体管，其一端连接到不可逆存储元件的另一端。 非易失性半导体存储装置包括：存储单元; 分别写入连接到第一晶体管和第二晶体管的字线和读字线; 分别写入连接到第一晶体管和第二晶体管的另一端的位线和读位线; 行解码器选择性地驱动写字线和读字线; 以及在写入数据时将读取位线充电到一定电压的写入干扰防止电路。
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7.发明授权Semiconductor memory device in which data is stored in nonvolatile state, by using semiconductor elements of metal oxide semiconductor (MOS) structure 有权通过使用金属氧化物半导体（MOS）结构的半导体元件，以非易失性状态存储数据的半导体存储器件公开(公告)号：US07613062B2
公开(公告)日：2009-11-03
申请号：US11738774
申请日：2007-04-23
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5256 , H01L27/101 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a memory element, a first data line and a second data line, a first selection transistor, and a second selection transistor. The memory element includes a semiconductor element of MOS structure in which data is programmed when an insulating film provided in the semiconductor element is broken down by application of a voltage thereto. The first and second data lines are connected to a sense amplifier. The first selection transistor is configured to connect the memory element to the first data line in order to program data in the memory element. The second selection transistor is configured to connect the memory element to the second data line in order to program data in the memory element and detect the data programmed in the memory element. The second selection transistor has a smaller gate-electrode width smaller than the first selection transistor.
摘要翻译： 半导体存储器件包括存储元件，第一数据线和第二数据线，第一选择晶体管和第二选择晶体管。 存储元件包括MOS结构的半导体元件，其中当半导体元件中提供的绝缘膜通过施加电压而被分解时数据被编程。 第一和第二数据线连接到读出放大器。 第一选择晶体管被配置为将存储元件连接到第一数据线，以便将数据编程在存储元件中。 第二选择晶体管被配置为将存储器元件连接到第二数据线，以便对存储元件中的数据进行编程，并检测存储元件中编程的数据。 第二选择晶体管具有比第一选择晶体管小的栅电极宽度。
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公开(公告)号：US07599206B2
公开(公告)日：2009-10-06
申请号：US12032110
申请日：2008-02-15
CPC分类号： G11C17/18
摘要： A non-volatile semiconductor storage device includes: one or more memory cells including anti-fuse elements capable of writing data by breaking down a gate insulation film of a MOS transistor with a high voltage; a sense node having its one end connected to each of the anti-fuse elements; a sense amplifier comparing the potential of the sense node with the reference potential and amplifying the difference therebetween, the sense amplifier being activated according to a sense-amplifier activation signal; an initialization circuit initializing the potential of the sense node according to an initialization signal; a control circuit outputting the initialization signal at a predetermined timing after input of an external signal input from the outside and outputting a first activation signal to activate the sense amplifier at a predetermined timing after input of the external signal; and a switching circuit outputting the first activation signal as the sense-amplifier activation signal when a normal data read operation is performed, and outputting an inverted version of the external signal as the sense-amplifier activation signal when a test execution is instructed for the one or more memory cells before the gate insulation film is broken down.
摘要翻译： 非挥发性半导体存储装置包括：一个或多个存储单元，包括能够通过以高电压分解MOS晶体管的栅极绝缘膜来写入数据的抗熔丝元件; 感测节点，其一端连接到每个反熔丝元件; 感测放大器将感测节点的电位与参考电位进行比较，并放大其间的差值，根据读出放大器激活信号来激活读出放大器; 初始化电路根据初始化信号初始化感测节点的电位; 控制电路在输入从外部输入的外部信号的输入之后的预定定时输出初始化信号，并输出第一激活信号，以在输入外部信号之后的预定定时激活读出放大器; 以及当执行正常数据读取操作时，输出作为读出放大器激活信号的第一激活信号的切换电路，并且当指示测试执行时，输出外部信号的反转版本作为读出放大器激活信号 或更多的存储单元在栅极绝缘膜破裂之前。
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9.发明申请SEMICONDUCTOR CHARGE PUMP USING MOS (METAL OXIDE SEMICONDUCTOR) TRANSISTOR FOR CURRENT RECTIFIER DEVICE 有权使用用于电流整流器器件的MOS（金属氧化物半导体）晶体管的半导体充电泵公开(公告)号：US20090201076A1
公开(公告)日：2009-08-13
申请号：US12424290
申请日：2009-04-15
申请人： Toshimasa Namekawa , Hiroshi Ito
发明人： Toshimasa Namekawa , Hiroshi Ito
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M2003/075 , H02M2003/077
摘要： A semiconductor charge pump includes a plurality of P-channel MOS transistors being connected in series, a plurality of first pumping capacitors one electrode of each of which is connected to a connection point of each of the P-channel MOS transistors, a clock signal generating circuit which generates first and second clock signals whose phases are different from each other by 180 degrees, the first and second clock signals being alternately supplied to the other electrodes of the first pumping capacitors. The semiconductor charge pump further includes a plurality of dynamic level converter circuits each including a resistor element and a second pumping capacitor and connected to each of gates of the P-channel MOS transistors.
摘要翻译： 半导体电荷泵包括串联连接的多个P沟道MOS晶体管，多个第一泵浦电容器，其中每一个的一个电极连接到每个P沟道MOS晶体管的连接点，产生时钟信号 电路，其产生相位彼此相差180度的第一和第二时钟信号，第一和第二时钟信号被交替地提供给第一泵浦电容器的其他电极。 半导体电荷泵还包括多个动态电平转换器电路，每个动态电平转换器电路各自包括电阻元件和第二泵浦电容器，并连接到P沟道MOS晶体管的每个栅极。
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10.发明授权Nonvolatile semiconductor memory device using nonvolatile storage elements to which data can be written only once 有权使用非易失性存储元件的非易失性半导体存储器件，数据只能写入一次公开(公告)号：US07505300B2
公开(公告)日：2009-03-17
申请号：US11733933
申请日：2007-04-11
IPC分类号： G11C17/00
CPC分类号： G11C17/18
摘要： A nonvolatile semiconductor memory device includes a nonvolatile storage element to which data is inhibited from being rewritten, a read operation control circuit which captures a read operation instruction signal in synchronization with an external input clock, and a write operation control circuit to which a write operation instruction signal is input asynchronously with the external input clock. The read operation instruction signal gives an instruction to start a read operation to read data out of the nonvolatile storage element, and the write operation instruction signal gives an instruction to start a write operation to write data to the nonvolatile storage element. The device further includes a reset circuit which resets an operation of the read operation control circuit upon receiving the write operation instruction signal.
摘要翻译： 非易失性半导体存储器件包括禁止数据被重写的非易失性存储元件，与外部输入时钟同步地捕获读取操作指令信号的读取操作控制电路以及写入操作的写入操作控制电路 指令信号与外部输入时钟异步输入。 读取操作指令信号给出开始读取操作以从非易失性存储元件读出数据的指令，并且写入操作指令信号给出开始写入操作以将数据写入非易失性存储元件的指令。 该装置还包括复位电路，其在接收到写入操作指令信号时复位读取操作控制电路的操作。
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