公开(公告)号：US06715093B1

公开(公告)日：2004-03-30

申请号：US09560194

申请日：2000-04-28

申请人： James C. Farmer ,  Kent A. Dickey

发明人： James C. Farmer ,  Kent A. Dickey

IPC分类号： G06F112

CPC分类号： G06F1/12

摘要： A method and apparatus are disclosed for allowing a system having multiple clock domains to be put into a known state to ensure repeatability during debugging tests. A global framing clock is created having a frequency equal to the lowest common denominator of all clocks in the system or to some divisor of thereof. At this frequency, the global framing clock ensures that it will have a rising edge at the same time that other clocks in the system have rising edges. The system clock and the global framing clock may be run throughout the system to integrated circuits. The global framing clock is used to control a system function, such as a reset or an interrupt function. When the system receives an asynchronous event, the global framing clock ensures that the event is not distributed to the system until the occurrence of a rising edge of the global framing clock. This ensures that the event will also be seen on a rising edge of every other system clock, which makes the event appear at the same time throughout the system. By ensuring that an asynchronous function, such as a reset function, appears at the same time throughout the system, the system becomes repeatable. That is, the clock states will be the same every time an asynchronous event is released to the system.

摘要翻译： 公开了一种允许将具有多个时钟域的系统置于已知状态以确保调试测试期间重复性的方法和装置。 创建一个全局成帧时钟，其频率等于系统中所有时钟的最低公分母或其除数。 在这个频率下，全局帧时钟可确保在系统中的其他时钟具有上升沿的同时具有上升沿。 系统时钟和全局帧时钟可以在整个系统中运行到集成电路。 全局帧时钟用于控制系统功能，如复位或中断功能。 当系统接收到异步事件时，全局帧时钟确保事件不会分发到系统，直到出现全局帧时钟的上升沿。 这确保了事件也将在每个其他系统时钟的上升沿被看到，这使得事件在整个系统中同时出现。 通过确保在整个系统中同时出现诸如复位功能的异步功能，系统变得可重复。 也就是说，每当异步事件被释放到系统时，时钟状态将是相同的。

公开(公告)号：US06473844B1

公开(公告)日：2002-10-29

申请号：US09562595

申请日：2000-04-29

申请人： James C. Farmer ,  Kent A. Dickey

发明人： James C. Farmer ,  Kent A. Dickey

IPC分类号： G06F1200

CPC分类号： G06F21/78

摘要： A system and method is described in which protected memory writes are achieved in single transaction without leaving open a window in time for erroneous data to corrupt space in a target register. A single data packet preferably includes both user data to be written to a target storage device or location as well as the key data for authorizing the writing of such user data. Key data is preferably calculated by manipulating user data contained in the same packet or transmission thereby simplifying a verification process conducted the controller associated with target storage location.

摘要翻译： 描述了一种系统和方法，其中在单个事务中实现受保护的存储器写入，而不会在时间上打开窗口以使错误的数据损坏目标寄存器中的空间。 单个数据分组优选地包括要写入目标存储设备或位置的用户数据以及用于授权写入这样的用户数据的密钥数据。 优选地通过操纵包含在相同分组或传输中的用户数据来计算密钥数据，从而简化了与目标存储位置相关联的控制器进行的验证过程。

公开(公告)号：US06725369B1

公开(公告)日：2004-04-20

申请号：US09560192

申请日：2000-04-28

申请人： James C. Farmer ,  Kent A. Dickey

发明人： James C. Farmer ,  Kent A. Dickey

IPC分类号： G06F700

CPC分类号： G06F7/768

摘要： A circuit for reconfiguring data into the particular data format for processors and system memory when operating in a particular dual-data format processing environment. The circuit uses an interface having read and write multiplexers to swap data bytes automatically, transforming data between big and little endian formats, based upon a control signal.

摘要翻译： 用于在特定的双数据格式处理环境中操作时将数据重新配置为处理器和系统存储器的特定数据格式的电路。 该电路使用具有读和写复用器的接口来自动交换数据字节，并根据控制信号在大端和小端格式之间转换数据。

公开(公告)号：US06625673B1

公开(公告)日：2003-09-23

申请号：US09562474

申请日：2000-05-01

申请人： Kent A. Dickey ,  Debendra Das Sharma

发明人： Kent A. Dickey ,  Debendra Das Sharma

IPC分类号： G06F1200

CPC分类号： G06F12/063 ,  G06F12/0661

摘要： An I/O mapping within a system memory of a computing system assigns a fixed address to each I/O device and I/O bridge in a larger address region of the system than the number of address bits of the I/O devices and/or the I/O bridges would allow. This fixed address assignment eliminates problems associated with fragmentation of I/O memory space of a conventional variable address assignment when I/O devices and/or I/O bridges are replaced on-line, i.e., hot-swapped. The I/O mapping utilizes a greater number of address bits than the address bits available from I/O devices to assign a much larger address space to each device by translating the larger number of bits address from the system to the smaller number of bits address of the I/O devices.

摘要翻译： 计算系统的系统存储器内的I / O映射将系统的较大地址区域中的每个I / O设备和I / O桥分配固定地址，比I / O设备的地址位数和/ 或I / O桥将允许。 这种固定地址分配消除了当I / O设备和/或I / O桥被在线更换，即热交换时，常规可变地址分配的I / O存储空间的分段相关的问题。 I / O映射利用比I / O设备可用的地址位数更多的地址位，通过将较大数量的位地址从系统转换为较少的位地址来为每个器件分配更大的地址空间 的I / O设备。

公开(公告)号：US06959352B1

公开(公告)日：2005-10-25

申请号：US09561815

申请日：2000-04-29

申请人： Kent A. Dickey

发明人： Kent A. Dickey

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： The present invention provides for a method and system for allowing non-trusted partitions in large scale computer system to safely interrupt a processor without the risk of corruption or loss of interconnect bandwidth, and without the need for inefficient hardwiring. In operation code preferably located outside of the central processor, interrupts coming from outside the partition into specific addresses for determination of allowability into the partition.

摘要翻译： 本发明提供一种方法和系统，用于允许大规模计算机系统中的不可信分区安全地中断处理器，而不会损坏或丢失互连带宽，并且不需要低效的硬连线。 在优选地位于中央处理器外部的操作代码中，从分区外部中断到特定地址以确定对分区的允许性。

公开(公告)号：US06651193B1

公开(公告)日：2003-11-18

申请号：US09562589

申请日：2000-04-29

申请人： Kent A. Dickey ,  Michael L. Ziegler

发明人： Kent A. Dickey ,  Michael L. Ziegler

IPC分类号： G06F1100

CPC分类号： G06F11/0796 ,  G06F11/004 ,  G06F11/0724 ,  G06F11/0772

摘要： The present invention provides for a method and system for ensuring error containment in packet based systems which are capable of large scaleability. In operation, an error bit travels with each data packet and if the bit is set, any device which receives the data packet acts to contain that packet. Thus, the error message travels only as far as the error data and does not stop processing at locations not affected by the error. Any system resource, upon receipt of a set error bit, must act to correct the fault.

摘要翻译： 本发明提供一种确保能够具有大的可扩展性的基于分组的系统中的错误容纳的方法和系统。 在操作中，错误位与每个数据包一起行进，并且如果该位被置位，则接收该数据包的任何设备用于包含该数据包。 因此，错误消息仅传送到错误数据的一个位置，并且不会在不受错误影响的位置停止处理。 任何系统资源在收到设置的错误位后都必须采取行动来纠正故障。

公开(公告)号：US5958072A

公开(公告)日：1999-09-28

申请号：US782964

申请日：1997-01-13

申请人： Edward M. Jacobs ,  Kent A. Dickey ,  Kathleen C. Nix

发明人： Edward M. Jacobs ,  Kent A. Dickey ,  Kathleen C. Nix

IPC分类号： G06F1/04 ,  G06F11/22 ,  G06F11/267 ,  G06F13/36 ,  G06F11/00 ,  G06F12/16 ,  G06F13/00

CPC分类号： G06F11/2273 ,  G06F11/221

摘要： A processor-to-memory interface (PMI) for a multiprocessor computer system and a computer testing method are disclosed. The multi-processor computer system provides a processor-to-memory-bus interface for each microprocessor. Each processor-to-memory-bus interface translates between microprocessor and bus protocols and manages respective level-2 (L2) caches. In addition, each interface includes test-event hardware that, when enabled causes test events to be generated with a predetermined repetition rate. The test events are selected for having a non-zero probability of causing system events that are complex, rare and non-fatal. These include assertions of "busy" and "wait" conditions and corrections of single-bit cache errors. The test-event hardware includes a timing generator that determines when test events are to be generated, an event-flag register that determines which events are to be generated, and a test-event generator that generates test-events at the times determined by the timing generator. The timing generator can include a down counter and a register for holding a value to be entered into the counter upon initialization and reset. So that cache error-correction logic can be tested, a cache manager includes a cache-error generator that can generate cache errors at times determined by said timing generator. The test-event hardware permits system events of interest to be repeatedly generated during a test procedure without repeated intervention by a test program. The hardware test-event generation simplifies test program design and allows faster testing throughput.

摘要翻译： 公开了一种用于多处理器计算机系统的处理器到存储器接口（PMI）和计算机测试方法。 多处理器计算机系统为每个微处理器提供处理器到存储器总线接口。 每个处理器到存储器总线接口在微处理器和总线协议之间进行转换，并管理相应的二级（L2）高速缓存。 另外，每个接口包括测试事件硬件，当被使能时，可以以预定的重复率生成测试事件。 选择测试事件具有导致复杂，罕见和非致命的系统事件的非零概率。 这些包括断言“忙”和“等待”条件和单位缓存错误的更正。 测试事件硬件包括一个定时发生器，用于确定何时生成测试事件，事件标志寄存器确定要生成哪些事件;以及测试事件发生器，其在由 定时发生器 定时发生器可以包括向下计数器和用于在初始化和复位时保持要输入到计数器中的值的寄存器。 因此，可以测试高速缓存错误校正逻辑，高速缓存管理器包括高速缓存错误发生器，其可以在由所述定时发生器确定的时间内产生高速缓存错误。 测试事件硬件允许感兴趣的系统事件在测试过程中重复产生，而不需要测试程序的反复干预。 硬件测试事件生成简化了测试程序设计，并允许更快的测试吞吐量。

公开(公告)号：US07478262B2

公开(公告)日：2009-01-13

申请号：US10664763

申请日：2003-09-17

申请人： Kent A. Dickey ,  Michael L. Ziegler

发明人： Kent A. Dickey ,  Michael L. Ziegler

IPC分类号： G06F11/00

CPC分类号： G06F11/0796 ,  G06F11/004 ,  G06F11/0724 ,  G06F11/0772

摘要： The present invention provides for a method and system for ensuring error containment in packet based systems which are capable of large scaleability. In operation, an error bit travels with each data packet and if the bit is set any device which receives the data packet acts to contain that packet. Thus, the error message travels only as far as the error data and does not stop processing at locations not affected by the error. Any system resource, upon receipt of a set error bit, must act to correct the fault.

摘要翻译： 本发明提供一种确保能够具有大的可扩展性的基于分组的系统中的错误容纳的方法和系统。 在操作中，错误位与每个数据分组一起传播，并且如果该位被置位，则接收数据分组的任何设备用于包含该分组。 因此，错误消息仅传送到错误数据的一个位置，并且不会在不受错误影响的位置停止处理。 任何系统资源在收到设置的错误位后都必须采取行动来纠正故障。

公开(公告)号：US06725387B1

公开(公告)日：2004-04-20

申请号：US09560904

申请日：2000-04-28

申请人： Dean T. Lindsay ,  Robert D. Snyder ,  Kent A. Dickey

发明人： Dean T. Lindsay ,  Robert D. Snyder ,  Kent A. Dickey

IPC分类号： G06F112

CPC分类号： G06F1/12

摘要： A method and apparatus are disclosed for improving the repeatability of a system during testing by ensuring that the machine state remains the same on every test. In particular, the system ensures that the polling block of a cross-bar chip is reset to the same point in the polling sequence and to the same port upon the start of every test. The system uses a global framing clock (“GFC”) as a common timing reference. Before executing test code, the system becomes idle and waits for a rising edge of the GFC. The system then sends a message across existing links from the monarch processor performing the test to a cache controller chip. The cache controller chip waits for a GFC edge and then sends a reset message to the cross-bar chip to reset the CSR polling block. The cross-bar chip receives the signal and resets the CSR polling block.

摘要翻译： 公开了一种用于通过确保机器状态在每次测试中保持相同的方式来提高测试期间系统的可重复性的方法和装置。 特别地，系统确保跨条形码片的轮询块在轮询序列中被重置为相同点，并且在每次测试开始时被重置到相同的端口。 系统使用全局成帧时钟（“GFC”）作为公共时序参考。 在执行测试代码之前，系统将空闲并等待GFC的上升沿。 然后，系统将从执行测试的君主处理器到高速缓存控制器芯片的现有链路发送消息。 高速缓存控制器芯片等待GFC边沿，然后将重置消息发送到交叉条芯片以重置CSR轮询块。 横杆芯片接收信号并复位CSR轮询块。

公开(公告)号：US06658543B2

公开(公告)日：2003-12-02

申请号：US10247098

申请日：2002-09-19

申请人： James C. Farmer ,  Kent A. Dickey

发明人： James C. Farmer ,  Kent A. Dickey

IPC分类号： G06F1200

CPC分类号： G06F21/78

摘要： A system and method for protecting memory space in a target storage device during a write operation in a computer system, comprising creating a single data packet, including user data that is to be written to said target storage device and key data that is used to establish authorization to store said user data; transmitting said single data packet to the target storage device; determining whether said key data is valid; writing said user data into said target storage device only when said key data is valid.

摘要翻译： 一种用于在计算机系统中的写入操作期间保护目标存储设备中的存储空间的系统和方法，包括创建单个数据分组，包括要写入所述目标存储设备的用户数据和用于建立用于建立的密钥数据的单个数据分组 授权存储所述用户数据; 将所述单个数据分组发送到所述目标存储设备; 确定所述密钥数据是否有效; 仅在所述密钥数据有效时将所述用户数据写入所述目标存储设备。