公开(公告)号：US07609185B2

公开(公告)日：2009-10-27

申请号：US12143708

申请日：2008-06-20

申请人： Kent Kernahan ,  Xuecheng Jin ,  Ping Lo ,  Ion E. Opris ,  Sorin Andrei Spanoche

发明人： Kent Kernahan ,  Xuecheng Jin ,  Ping Lo ,  Ion E. Opris ,  Sorin Andrei Spanoche

IPC分类号： H03M1/10

CPC分类号： H03M1/38

摘要： Methods are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption. A predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal.

摘要翻译： 公开了用于在较短时间内和/或具有较少功耗的模拟信号转换中执行的方法。 预测猜测作为数字第一信号提供。 数字第一信号被转换（D / A）到对应的模拟猜测信号。 比较模拟猜测信号和接收的模拟输入采样信号。 比较结果用于在下一个周期中提高初始提供的猜测。 如果初始猜测在模拟输入采样信号的实际幅度的一定范围内，则消耗更少的周期和更少的功率。

公开(公告)号：US07405689B2

公开(公告)日：2008-07-29

申请号：US11316636

申请日：2005-12-21

申请人： Kent Kernahan ,  Xuecheng Jin ,  Ping Lo ,  Ion E. Opris ,  Sorin Andrei Spanoche

发明人： Kent Kernahan ,  Xuecheng Jin ,  Ping Lo ,  Ion E. Opris ,  Sorin Andrei Spanoche

IPC分类号： H03M1/12

CPC分类号： H03M1/38

摘要： Methods and devices perform analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. A predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal. In one embodiment, a digital modeler is used to model a process underlying the analog input sample signal to thereby provide fairly good guesses.

摘要翻译： 方法和设备在较短的时间内和/或具有比使用基于二进制搜索的常规顺序近似方法的可比较模数转换的功耗更少的时间和/或执行模数转换。 预测猜测作为数字第一信号提供。 数字第一信号被转换（D / A）到对应的模拟猜测信号。 如果初始猜测在模拟输入采样信号的实际幅度的一定范围内，则消耗更少的周期和更少的功率。 在一个实施例中，数字建模器用于对模拟输入采样信号的过程进行建模，从而提供相当好的猜测。

公开(公告)号：US20060158365A1

公开(公告)日：2006-07-20

申请号：US11316636

申请日：2005-12-21

申请人： Kent Kernahan ,  Xuecheng Jin ,  Ping Lo ,  Ion Opris ,  Sorin Spanoche

发明人： Kent Kernahan ,  Xuecheng Jin ,  Ping Lo ,  Ion Opris ,  Sorin Spanoche

IPC分类号： H03M1/12

CPC分类号： H03M1/38

摘要： Methods and devices are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. In one embodiment, a predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal. In one embodiment, a digital modeler is used to model a process underlying the analog input sample signal and to thereby provide fairly good guesses.

摘要翻译： 公开了用于在较短时间内和/或具有比使用基于二进制搜索的常规顺序近似方法的可比较模数转换的功耗更少的时间和/或执行模数转换的方法和装置。 在一个实施例中，预测猜测被提供为数字第一信号。 数字第一信号被转换（D / A）到对应的模拟猜测信号。 比较模拟猜测信号和接收的模拟输入采样信号。 比较结果用于在下一个周期中提高初始提供的猜测。 如果初始猜测在模拟输入采样信号的实际幅度的一定范围内，则消耗更少的周期和更少的功率。 在一个实施例中，数字建模器用于对模拟输入采样信号的过程进行建模，从而提供相当好的猜测。

公开(公告)号：US07336058B1

公开(公告)日：2008-02-26

申请号：US11671793

申请日：2007-02-06

申请人： Ping Lo ,  Xuecheng Jin

发明人： Ping Lo ,  Xuecheng Jin

IPC分类号： G05F1/40

CPC分类号： G05F1/575

摘要： A low dropout (LDO) voltage regulator having more than one LDO modules, each LDO module having a frequency response adapted to a certain range of output frequency. The LDO voltage regulator can provide a gain over a broad range of operating frequency by combining output current from each LDO module and providing the combined current at an output of the LDO voltage regulator. The LDO voltage regulator further comprises a load monitor coupled to the LDO modules for disabling some of the LDO modules to reduce power consumption of the LDO voltage regulator.

摘要翻译： 具有多于一个LDO模块的低压降（LDO）稳压器，每个LDO模块具有适应于一定范围的输出频率的频率响应。 LDO稳压器可以通过组合来自每个LDO模块的输出电流并在LDO稳压器的输出端提供组合电流，在宽范围的工作频率范围内提供增益。 LDO稳压器还包括耦合到LDO模块的负载监视器，用于禁用一些LDO模块以降低LDO电压调节器的功耗。

公开(公告)号：US07474130B1

公开(公告)日：2009-01-06

申请号：US11671810

申请日：2007-02-06

申请人： Ping Lo ,  Xuecheng Jin

发明人： Ping Lo ,  Xuecheng Jin

IPC分类号： H02M11/00 ,  H03L7/06

CPC分类号： H03L7/099 ,  H03L1/022

摘要： A voltage-to-current converter providing an output current with compensation for process-voltage-temperature (PVT) variations of a component in the voltage-to-current converter. The voltage-to-current converter includes a first voltage-to-current converter branch, a second voltage-to-current converter branch, and a compensation current path. The first voltage-to-current converter provides a first current to the output of the voltage-to-current converter based on a variable control voltage. The second voltage-to-current converter branch provides a second current based on a fixed voltage. The compensation current path provides a compensation current from the second voltage-to-current branch to the first voltage-to-current converter branch compensating variations in the first current caused by the PVT variations of the component in the first voltage-to-current converter branch.

摘要翻译： 电压 - 电流转换器提供输出电流，补偿电压 - 电流转换器中部件的过程电压 - 温度（PVT）变化。 电压 - 电流转换器包括第一电压 - 电流转换器分支，第二电压 - 电流转换器分支和补偿电流路径。 第一电压 - 电流转换器基于可变控制电压向电压 - 电流转换器的输出提供第一电流。 第二电压 - 电流转换器分支提供基于固定电压的第二电流。 补偿电流路径提供从第二电压 - 电流分支到第一电压 - 电流转换器分支的补偿电流，补偿由第一电压 - 电流转换器中的组件的PVT变化引起的第一电流的变化 科。

公开(公告)号：US5933385A

公开(公告)日：1999-08-03

申请号：US903720

申请日：1997-07-31

申请人： Yong Jiang ,  Ping Lo

发明人： Yong Jiang ,  Ping Lo

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： A flexible memory controller capable of performing any combination of read, write and deselect operations is described. The present invention can store two pending write or read operations and perform a third write or read operation. In a ZBT SRAM embodiment the memory controller has three address registers, two data registers, and two comparators. Addresses for pending memory access operations are shifted in the address registers so that memory access addresses can be stored without overwriting the memory addresses for the pending operations. Similarly, data is shifted in the data registers to ensure that data remains available for pending memory access operations. The specific register operations are controlled by a thirteen state state machine. The thirteen states and the relationships between the states are defined to enable the memory controller to perform any combination of read, write and deselect operations without inserting idle cycles. When a read address matches the address of a pending write operation it indicates that the data that the read address is intended to retrieve has not yet been written to the memory array. The data for this read operation may be in one or more places including the memory I/O pins, either of the two data registers, or inside the memory. The state machine includes a series of logical comparisons to identify the location of the desired data. After the data location is determined the data is loaded into the output register.

摘要翻译： 描述能够执行读取，写入和取消选择操作的任何组合的灵活的存储器控​​制器。 本发明可以存储两个待处理的写入或读取操作并执行第三次写入或读取操作。 在ZBT SRAM实施例中，存储器控制器具有三个地址寄存器，两个数据寄存器和两个比较器。 待处理的存储器访问操作的地址在地址寄存器中被移位，使得可以存储存储器访问地址而不覆盖待处理操作的存储器地址。 类似地，数据在数据寄存器中移位，以确保数据保持可用于待机内存访问操作。 特定的寄存器操作由十三个状态机控制。 定义了十三个状态和状态之间的关系，以使内存控制器能够执行读取，写入和取消选择操作的任何组合，而不会插入空闲周期。 当读取地址与待处理写入操作的地址匹配时，它指示读取地址要检索的数据尚未写入存储器阵列。 该读取操作的数据可以在一个或多个位置，包括存储器I / O引脚，两个数据寄存器中的任一个或存储器内。 状态机包括一系列逻辑比较，以识别所需数据的位置。 确定数据位置后，将数据加载到输出寄存器中。