Semiconductor device
    3.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号:US07884476B2

    公开(公告)日:2011-02-08

    申请号:US12364228

    申请日:2009-02-02

    申请人: Keun Soo Park

    发明人: Keun Soo Park

    IPC分类号: H01L23/485

    摘要: Embodiments relate to a semiconductor device. In embodiments, the semiconductor device may include a semiconductor substrate having a first metal line; a pre-metal dielectric (PMD) layer over the first metal line on the semiconductor substrate; a first metal layer formed in a first contact hole in the PMD layer; a second metal layer formed in a second contact hole in the PMD layer; and a second metal line electrically connected to the first and second metal layers, respectively, over the PMD layer, wherein the first and second metal layers are located at prescribed positions and configured to be electrically connected to the first metal line.

    摘要翻译: 实施例涉及一种半导体器件。 在实施例中,半导体器件可以包括具有第一金属线的半导体衬底; 在半导体衬底上的第一金属线上的预金属电介质(PMD)层; 在PMD层的第一接触孔中形成的第一金属层; 形成在PMD层的第二接触孔中的第二金属层; 以及分别在所述PMD层上电连接到所述第一和第二金属层的第二金属线,其中所述第一和第二金属层位于规定位置并且被配置为电连接到所述第一金属线。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US07485578B2

    公开(公告)日:2009-02-03

    申请号:US11617057

    申请日:2006-12-28

    申请人: Keun Soo Park

    发明人: Keun Soo Park

    IPC分类号: H01L21/44 H01L23/48

    CPC分类号: H01L21/76844 H01L21/76846

    摘要: Embodiments relate to a semiconductor device and a method of fabricating semiconductor device, that may uniformly form a barrier layer in a via hole to thus prevent layers from being broken. In embodiments, a method of fabricating a semiconductor device may include forming an interlayer dielectric layer on a substrate, forming via holes selectively on the interlayer dielectric layer, forming a first metal layer on a top surface of the substrate including inner portion of the via hole, forming spacers on sides of the via holes by etching back the first metal layer, forming a second metal layer on the substrate including the spacer, and forming a tungsten layer by depositing tungsten on the second metal layer.

    摘要翻译: 实施例涉及半导体器件和制造半导体器件的方法,其可以在通孔中均匀地形成阻挡层,从而防止层破裂。 在实施例中,制造半导体器件的方法可以包括在衬底上形成层间电介质层,在层间电介质层上选择性地形成通路孔,在衬底的顶表面上形成第一金属层,包括通孔内部 通过蚀刻第一金属层在通孔的侧面上形成间隔物,在包括间隔物的基片上形成第二金属层,并通过在第二金属层上沉积钨形成钨层。

    Semiconductor device and method for manufacturing the same
    5.
    发明申请
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号:US20070148801A1

    公开(公告)日:2007-06-28

    申请号:US11641792

    申请日:2006-12-20

    申请人: Keun Soo Park

    发明人: Keun Soo Park

    IPC分类号: H01L21/00

    摘要: A method for manufacturing a semiconductor device includes the steps of: forming a gate on a semiconductor substrate; sequentially stacking a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate including the gate; forming a first photoresist layer pattern on the second oxide layer; forming a second oxide layer pattern by wet etching the second oxide layer by using the first photoresist layer pattern as a mask; forming a nitride layer pattern by dry etching the nitride layer using the second oxide layer pattern as a mask; and forming a first oxide layer pattern by etching the first oxide layer using the nitride layer pattern as a mask.

    摘要翻译: 一种制造半导体器件的方法包括以下步骤:在半导体衬底上形成栅极; 在包括栅极的半导体衬底上依次层叠第一氧化物层,氮化物层和第二氧化物层; 在所述第二氧化物层上形成第一光致抗蚀剂图案; 通过使用第一光致抗蚀剂层图案作为掩模,通过湿法蚀刻第二氧化物层来形成第二氧化物层图案; 通过使用第二氧化物层图案作为掩模将氮化物层干蚀刻来形成氮化物层图案; 以及通过使用氮化物层图案作为掩模蚀刻第一氧化物层来形成第一氧化物层图案。

    Semiconductor device and method for manufacturing the same
    6.
    发明授权
    Semiconductor device and method for manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号:US07709372B2

    公开(公告)日:2010-05-04

    申请号:US11641037

    申请日:2006-12-19

    申请人: Keun Soo Park

    发明人: Keun Soo Park

    IPC分类号: H01L21/4763

    摘要: A method of manufacturing a metal wiring in a semiconductor device includes: forming a via hole by selectively etching an interlayer insulating layer formed on a first metal layer; sequentially forming a first barrier metal layer and a second metal layer on the interlayer insulating layer; etching the first barrier metal layer and the second metal layer in the via hole to a predetermined depth together with selectively etching a surface of the second metal layer; forming a silicon layer on the first barrier metal and the second metal to a predetermined height; forming a second barrier metal layer on the interlayer insulating layer; forming a third metal layer on the second barrier metal layer; and forming a second barrier metal pattern and a third metal layer pattern by patterning the second barrier metal layer and the third metal layer.

    摘要翻译: 在半导体器件中制造金属布线的方法包括:通过选择性地蚀刻形成在第一金属层上的层间绝缘层来形成通孔; 在层间绝缘层上依次形成第一阻挡金属层和第二金属层; 在选择性蚀刻第二金属层的表面的同时,将通孔中的第一阻挡金属层和第二金属层蚀刻到预定深度; 在所述第一阻挡金属和所述第二金属上形成硅层至预定高度; 在所述层间绝缘层上形成第二阻挡金属层; 在所述第二阻挡金属层上形成第三金属层; 以及通过图案化所述第二阻挡金属层和所述第三金属层来形成第二阻挡金属图案和第三金属层图案。

    Antifuse having uniform dielectric thickness and method for fabricating the same
    7.
    发明授权
    Antifuse having uniform dielectric thickness and method for fabricating the same 失效
    具有均匀介电厚度的防腐剂及其制造方法

    公开(公告)号:US07569429B2

    公开(公告)日:2009-08-04

    申请号:US11324006

    申请日:2005-12-29

    申请人: Keun Soo Park

    发明人: Keun Soo Park

    IPC分类号: H01L21/82

    摘要: Disclosed are an antifuse having a uniform amorphous silicon (antifuse material) thickness and a method for fabricating such an antifuse device. The antifuse is located between overlying and underlying conductive layers, and includes: a contact and/or via hole in an insulating layer on the underlying conductive layer; a lower metal layer contacting inner surfaces of the contact and/or via hole and a top surface of the insulating layer; a filling layer contacting the lower barrier metal layer and at least partially filling the contact and/or via hole; an antifuse material layer contacting a top surface of the filling layer and a part of the lower metal layer; and an upper metal layer on the antifuse material layer.

    摘要翻译: 公开了具有均匀非晶硅(反熔丝材料)厚度的反熔丝以及制造这种反熔丝装置的方法。 反熔丝位于上面和下面的导电层之间,并且包括:在下面的导电层上的绝缘层中的接触和/或通孔; 接触和/或通孔的内表面与绝缘层的顶表面接触的下金属层; 接触所述下阻挡金属层并且至少部分地填充所述接触和/或通孔的填充层; 与所述填充层的顶表面和所述下金属层的一部分接触的反熔丝材料层; 和反熔丝材料层上的上金属层。

    Semiconductor device and method for manufacturing the same
    8.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号:US07566660B2

    公开(公告)日:2009-07-28

    申请号:US11641792

    申请日:2006-12-20

    申请人: Keun Soo Park

    发明人: Keun Soo Park

    IPC分类号: H01L21/44 H01L21/469

    摘要: A method for manufacturing a semiconductor device includes the steps of: forming a gate on a semiconductor substrate; sequentially stacking a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate including the gate; forming a first photoresist layer pattern on the second oxide layer; forming a second oxide layer pattern by wet etching the second oxide layer by using the first photoresist layer pattern as a mask; forming a nitride layer pattern by dry etching the nitride layer using the second oxide layer pattern as a mask; and forming a first oxide layer pattern by etching the first oxide layer using the nitride layer pattern as a mask.

    摘要翻译: 一种制造半导体器件的方法包括以下步骤:在半导体衬底上形成栅极; 在包括栅极的半导体衬底上依次层叠第一氧化物层,氮化物层和第二氧化物层; 在所述第二氧化物层上形成第一光致抗蚀剂图案; 通过使用第一光致抗蚀剂层图案作为掩模,通过湿法蚀刻第二氧化物层来形成第二氧化物层图案; 通过使用第二氧化物层图案作为掩模将氮化物层干蚀刻来形成氮化物层图案; 以及通过使用氮化物层图案作为掩模蚀刻第一氧化物层来形成第一氧化物层图案。

    SHALLOW TRENCH ISOLATION REGION IN SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    9.
    发明申请
    SHALLOW TRENCH ISOLATION REGION IN SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE 失效
    半导体器件中的低温分离区和制造方法

    公开(公告)号:US20070148909A1

    公开(公告)日:2007-06-28

    申请号:US11611551

    申请日:2006-12-15

    申请人: Keun Soo Park

    发明人: Keun Soo Park

    IPC分类号: H01L21/76

    CPC分类号: H01L21/76224

    摘要: A method of forming a device isolation region in a semiconductor device is capable of completely removing an oxide layer for trench formation in a central region of the semiconductor device without forming a moat in an edge region. The method begins with forming a sacrificial oxide and sacrificial nitride layer over a semiconductor substrate. Trenches are etched in the nitride layer, the oxide layer and the substrate in the central and edge regions, respectively. The trenches are filled with an oxide layer. The oxide layer is then polished until the sacrificial nitride layer formed in the edge region is exposed, to form a first device isolation region filling a first trench and a second device isolation region pattern filling a second trench and covering the second region. A photoresist pattern is formed over the first device isolation region and the second device isolation region pattern. The second device isolation region pattern is partially etched using the photoresist pattern as a mask to form a second device isolation region.

    摘要翻译: 在半导体器件中形成器件隔离区域的方法能够在半导体器件的中心区域中完全去除用于沟槽形成的氧化物层,而不会在边缘区域中形成护环。 该方法开始于在半导体衬底上形成牺牲氧化物和牺牲氮化物层。 在中心区域和边缘区域中的氮化物层,氧化物层和衬底分别蚀刻沟槽。 沟槽填充有氧化物层。 然后抛光氧化层直到形成在边缘区域中的牺牲氮化物层被暴露,以形成填充第一沟槽的第一器件隔离区域和填充第二沟槽并覆盖第二区域的第二器件隔离区域图案。 在第一器件隔离区域和第二器件隔离区域图案上形成光致抗蚀剂图案。 使用光致抗蚀剂图案作为掩模来部分地蚀刻第二器件隔离区域图案以形成第二器件隔离区域。

    Shallow trench isolation region in semiconductor device and method of manufacture
    10.
    发明授权
    Shallow trench isolation region in semiconductor device and method of manufacture 失效
    半导体器件中浅沟槽隔离区及其制造方法

    公开(公告)号:US07622360B2

    公开(公告)日:2009-11-24

    申请号:US11611551

    申请日:2006-12-15

    申请人: Keun Soo Park

    发明人: Keun Soo Park

    IPC分类号: H01L21/76

    CPC分类号: H01L21/76224

    摘要: A method of forming a device isolation region in a semiconductor device is capable of completely removing an oxide layer for trench formation in a central region of the semiconductor device without forming a moat in an edge region. The method begins with forming a sacrificial oxide and sacrificial nitride layer over a semiconductor substrate. Trenches are etched in the nitride layer, the oxide layer and the substrate in the central and edge regions, respectively. The trenches are filled with an oxide layer. The oxide layer is then polished until the sacrificial nitride layer formed in the edge region is exposed, to form a first device isolation region filling a first trench and a second device isolation region pattern filling a second trench and covering the second region. A photoresist pattern is formed over the first device isolation region and the second device isolation region pattern. The second device isolation region pattern is partially etched using the photoresist pattern as a mask to form a second device isolation region.

    摘要翻译: 在半导体器件中形成器件隔离区域的方法能够在半导体器件的中心区域中完全去除用于沟槽形成的氧化物层,而不会在边缘区域中形成护环。 该方法开始于在半导体衬底上形成牺牲氧化物和牺牲氮化物层。 在中心区域和边缘区域中的氮化物层,氧化物层和衬底分别蚀刻沟槽。 沟槽填充有氧化物层。 然后抛光氧化层直到形成在边缘区域中的牺牲氮化物层被暴露,以形成填充第一沟槽的第一器件隔离区域和填充第二沟槽并覆盖第二区域的第二器件隔离区域图案。 在第一器件隔离区域和第二器件隔离区域图案上形成光致抗蚀剂图案。 使用光致抗蚀剂图案作为掩模来部分地蚀刻第二器件隔离区域图案以形成第二器件隔离区域。