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1.发明授权System, method and storage medium for providing data caching and data compression in a memory subsystem 失效用于在存储器子系统中提供数据缓存和数据压缩的系统，方法和存储介质公开(公告)号：US07480759B2
公开(公告)日：2009-01-20
申请号：US11772922
申请日：2007-07-03
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0802 , G06F2212/401
摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.
摘要翻译： 包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。 一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。 存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。 第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。
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2.发明授权System, method and storage medium for providing data caching and data compression in a memory subsystem 有权用于在存储器子系统中提供数据缓存和数据压缩的系统，方法和存储介质公开(公告)号：US07451273B2
公开(公告)日：2008-11-11
申请号：US11780048
申请日：2007-07-19
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0802 , G06F2212/401
摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.
摘要翻译： 包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。 一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。 存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。 第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。
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3.发明授权System, method and storage medium for providing data caching and data compression in a memory subsystem 失效用于在存储器子系统中提供数据缓存和数据压缩的系统，方法和存储介质公开(公告)号：US07277988B2
公开(公告)日：2007-10-02
申请号：US10977846
申请日：2004-10-29
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0802 , G06F2212/401
摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.
摘要翻译： 包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。 一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。 存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。 第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。
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公开(公告)号：US20100005218A1
公开(公告)日：2010-01-07
申请号：US12165816
申请日：2008-07-01
IPC分类号： G06F12/06
CPC分类号： G06F13/4234
摘要： A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device, and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. The memory channel includes unidirectional downstream link segments coupled to the memory controller and operable for transferring configurable data frames. The memory channel further includes unidirectional upstream link segments coupled to the memory controller and operable for transferring data frames.
摘要翻译： 提供了一种用于提供增强级联互连存储器系统的系统，存储器集线器设备，方法和设计结构。 该系统包括存储器控制器，存储器通道，耦合到存储器通道的存储器集线器设备，以经由另一个存储器集线器设备的直接连接和级联互连中的一个与存储器控制器进行通信，以及与存储控制器通信的多个存储器设备 存储器控制器经由一个或多个级联互连的存储器集线器设备。 存储器通道包括耦合到存储器控制器并且可操作用于传输可配置数据帧的单向下游链路段。 存储器通道还包括耦合到存储器控制器并且可操作用于传送数据帧的单向上游链路段。
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公开(公告)号：US20080005496A1
公开(公告)日：2008-01-03
申请号：US11383989
申请日：2006-05-18
IPC分类号： G06F13/00
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.
摘要翻译： 公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。 出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。 第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。
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6.发明申请PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY 有权在具有INDETERMINATE读取数据延迟的存储器系统中提供帧起始指示公开(公告)号：US20120151171A1
公开(公告)日：2012-06-14
申请号：US13397819
申请日：2012-02-16
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A memory system, having indeterminate read data latency, that includes a memory controller and one or more hub devices. The memory controller is configured for receiving data transfers via an upstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting a frame start indicator. The data frame includes an identification tag that is utilized by the memory controller to associate the data frame with a corresponding read instruction issued by the memory controller. The one or more hub devices are in communication with the memory controller in a cascade interconnect manner via the upstream channel and a downstream channel. Each hub device is configured for receiving the data transfers via the upstream channel or the downstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting the frame start indicator.
摘要翻译： 具有不确定的读取数据延迟的存储器系统，其包括存储器控制器和一个或多个集线器设备。 存储器控制器被配置为经由上游信道接收数据传输，并且通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。 数据帧包括由存储器控制器用于将数据帧与由存储器控制器发出的相应读取指令相关联的识别标签。 一个或多个集线器设备经由上游信道和下游信道以级联互连方式与存储器控制器通信。 每个集线器设备被配置用于经由上游信道或下游信道接收数据传输，并且用于通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。
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公开(公告)号：US07447831B2
公开(公告)日：2008-11-04
申请号：US11383989
申请日：2006-05-18
IPC分类号： G06F13/14
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.
摘要翻译： 公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。 出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。 第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。
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8.发明授权Providing frame start indication in a memory system having indeterminate read data latency 有权在具有不确定的读数据延迟的存储器系统中提供帧起始指示公开(公告)号：US08327105B2
公开(公告)日：2012-12-04
申请号：US13397819
申请日：2012-02-16
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A memory system, having indeterminate read data latency, that includes a memory controller and one or more hub devices. The memory controller is configured for receiving data transfers via an upstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting a frame start indicator. The data frame includes an identification tag that is utilized by the memory controller to associate the data frame with a corresponding read instruction issued by the memory controller. The one or more hub devices are in communication with the memory controller in a cascade interconnect manner via the upstream channel and a downstream channel. Each hub device is configured for receiving the data transfers via the upstream channel or the downstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting the frame start indicator.
摘要翻译： 具有不确定的读取数据延迟的存储器系统，其包括存储器控制器和一个或多个集线器设备。 存储器控制器被配置为经由上游信道接收数据传输，并且通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。 数据帧包括由存储器控制器用于将数据帧与由存储器控制器发出的相应读取指令相关联的识别标签。 一个或多个集线器设备经由上游信道和下游信道以级联互连方式与存储器控制器通信。 每个集线器设备被配置用于经由上游信道或下游信道接收数据传输，并且用于通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。
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9.发明申请PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY 有权在具有INDETERMINATE读取数据延迟的存储器系统中提供帧起始指示公开(公告)号：US20120151172A1
公开(公告)日：2012-06-14
申请号：US13397827
申请日：2012-02-16
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method for providing frame start indication that includes receiving a data transfer via a channel in a memory system. The receiving is in response to a request, and at an indeterminate time relative to the request. It is determined whether the data transfer includes a frame start indicator. The data transfer and “n” subsequent data transfers are captured in response to determining that the data transfer includes a frame start indicator. The data transfer and the “n” subsequent data transfers make up a data frame, where “n” is greater than zero.
摘要翻译： 一种用于提供帧开始指示的方法，包括经由存储器系统中的信道接收数据传送。 接收是响应于请求，并且在相对于请求的不确定的时间。 确定数据传输是否包括帧起始指示符。 响应于确定数据传输包括帧起始指示符，捕获数据传输和“n”个后续数据传输。 数据传输和“n”个后续数据传输构成数据帧，其中“n”大于零。
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10.发明授权Method and system for providing identification tags in a memory system having indeterminate data response times 有权在具有不确定的数据响应时间的存储器系统中提供识别标签的方法和系统公开(公告)号：US08151042B2
公开(公告)日：2012-04-03
申请号：US11843271
申请日：2007-08-22
IPC分类号： G06F12/06
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method and system for providing identification tags in a memory system having indeterminate data response times. An exemplary embodiment includes a memory controller in a memory system. The memory controller includes a mechanism for receiving data packets via an upstream channel, the data packets including upstream identification tags. The memory controller also includes a mechanism having instructions for facilitating determining if a received data packet is in response to a request from the memory controller. Input to the determining includes an upstream identification tag included in the received data packet. If the received data packet is determined to be in response to a request from the memory controller, then the received data packet is matched to the request, thereby allowing the memory controller to operate with indeterminate data response times.
摘要翻译： 一种用于在具有不确定的数据响应时间的存储器系统中提供识别标签的方法和系统。 示例性实施例包括存储器系统中的存储器控制器。 存储器控制器包括用于经由上游信道接收数据分组的机制，所述数据分组包括上行识别标签。 存储器控制器还包括具有用于有助于确定接收的数据分组是否响应于来自存储器控制器的请求的指令的机制。 确定的输入包括包含在接收的数据分组中的上游标识标签。 如果接收到的数据分组被确定为响应于来自存储器控制器的请求，则接收的数据分组与该请求匹配，从而允许存储器控制器以不确定的数据响应时间进行操作。
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