摘要:
An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.
摘要:
An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.
摘要:
A bus system is provided for implantable medical devices. The bus system provides for flexible and reliable communication between subsystems in an implantable medical device. The bus system facilitates a wide variety of communications between various subsystems. These various subsystems can include one or more sensing devices, processors, data storage devices, patient alert devices, power management devices, signal processing and other devices implemented to perform a variety of different functions.
摘要:
Cyclic redundancy calculations are provided by operating on a data stream, e.g., a data stream in an implantable medical device, to perform a polynomial division thereon using one of a first cyclic redundancy code generator polynomial and a second cyclic redundancy code generator polynomial. The first cyclic redundancy code generator polynomial is a higher order polynomial than the second cyclic redundancy code generator polynomial and contains all terms of the second cyclic redundancy code generator polynomial. The polynomial division may be implemented using linear feedback shift register circuitry and circuitry to select between the use of the first or second cyclic redundancy code generator polynomial.
摘要:
A signal processor operates on a microprocessor or state machine based system to ensure that the central processing unit (CPU) and pulse generator (PG) have finished their instructions before allowing a new transition on the system master clock. The CPU and PG contain circuitry which allows them to indicate when they are busy. These signals are fed to the signal processor to indicate when the CPU and PG are ready to start another instruction. The signal processor functions to prevent a noise glitch on the system clock from causing another operation to start before the one in process has finished. The output of the signal processor becomes the master clock signal used by the system.
摘要:
A bus system is provided for implantable medical devices. The bus system provides for flexible and reliable communication between subsystems in an implantable medical device. The bus system facilitates a wide variety of communications between various subsystems. These various subsystems can include one or more sensing devices, processors, data storage devices, patient alert devices, power management devices, signal processing and other devices implemented to perform a variety of different functions.
摘要:
A method and apparatus including conditional add and conditional add/subtract instructions are provided for use in the instruction set of a medical device instruction processor. More specifically, the conditional add and add/subtract instructions are provided to add two operands if a predetermined condition is satisfied within the instruction processor hardware. Additionally, the conditional add/subtract instruction may be used to subtract one operand from another operand if the predetermined condition is not satisfied. These instructions are adapted for use in implementing an efficient, interruptible, firmware-controlled multiplication or division mechanism. The inventive system allows multiplication or division operations to be interrupted at various intermediate points during the multiplication or division operation to thereby reducing interrupt latency.
摘要:
A peripheral memory patch apparatus for attachment to a patient's skin includes a high capacity memory for storing physiologic data uplinked from an implantable medical device. A resilient substrate provides support for a memory, microprocessor, receiver, and other electronic components. The substrate flexes in a complimentary manner in response to a patient's body movements. The substrate is affixed to the patient's skin with the use of an adhesive which provides for comfort and wearability. The low profile peripheral patch apparatus is preferably similar in size and shape to a standard bandage, and may be attached to the patient's skin in an inconspicuous location. A status indicator provides for a visual, verbal, or tactile indication of the operational status of the peripheral memory patch. Uplinking of physiologic telemetry data from the internal memory of an implantable medical device to the peripheral memory patch is initiated in response to a transfer signal produced by the peripheral memory patch. The transfer signal may be generated by the implantable medical device or upon actuation of a switch by the patient. Various telemetry techniques including radio frequency, acoustic, and body bus telemetry techniques, may be employed to transfer information between the implantable medical device and the peripheral memory patch.