公开(公告)号：US06469350B1

公开(公告)日：2002-10-22

申请号：US09682868

申请日：2001-10-26

Applicant: William F. Clark, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  Minh H. Tong

Inventor： William F. Clark, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  Minh H. Tong

IPC: H01L2701

CPC classification number: H01L29/66772 ,  H01L21/743 ,  H01L29/66545 ,  H01L29/78612 ,  H01L29/78618 ,  Y10S148/077 ,  Y10S148/15

Abstract: A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes field effect transistor 124 comprising at least body region 127 and diffusion regions 132; buried interconnect plane 122 optionally self-aligned to diffusion regions 132 and in contact with body region 127; isolation oxide region 118 between diffusion regions 132 and buried interconnect plane 122; and buried oxide layer 104 present beneath buried interconnect plane 122.

Abstract translation: 本文公开了在绝缘体上硅衬底上制造并具有活性阱方案的半导体器件以及制造这种器件的包括非自对准和自对准的方法。 半导体器件包括至少包括体区127和扩散区132的场效应晶体管124; 埋入的互连平面122可选地与扩散区132自对准并与体区127接触; 扩散区域132和掩埋互连平面122之间的隔离氧化物区域118; 和掩埋的互连平面122下方的掩埋氧化物层104。

公开(公告)号：US6100564A

公开(公告)日：2000-08-08

申请号：US163950

申请日：1998-09-30

Applicant: Andres Bryant ,  Edward J. Nowak ,  Minh H. Tong

Inventor： Andres Bryant ,  Edward J. Nowak ,  Minh H. Tong

IPC: H01L21/335 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L27/01 ,  H01L29/10

CPC classification number: H01L27/0288 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002

Abstract: An SOI pass-gate disturb solution for an N-type MOSFET wherein a resistor is connected between the gate and the body of the FET to eliminate the disturb condition. The FET is fabricated in a substrate having a source, a drain and a gate, wherein the body of the field effect transistor is electrically floating and the transistor is substantially electrically isolated from the substrate. A high resistance path is provided coupling the electrically floating body of the FET to the gate, such that the body discharges to a low state before significant thermal charging can occur when the gate is low, and thus prevents the accumulation of a charge on the body when the transistor is off. The resistance of the high resistance path is preferably approximately 10.sup.10 Ohms-um divided by the width of the pass-gate.

公开(公告)号：US5959335A

公开(公告)日：1999-09-28

申请号：US159307

申请日：1998-09-23

Applicant: Andres Bryant ,  William F. Clark ,  John J. Ellis-Monaghan ,  Edward P. Maciejewski ,  Edward J. Nowak ,  Wilbur D. Pricer ,  Minh H. Tong

Inventor： Andres Bryant ,  William F. Clark ,  John J. Ellis-Monaghan ,  Edward P. Maciejewski ,  Edward J. Nowak ,  Wilbur D. Pricer ,  Minh H. Tong

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/7841 ,  H01L27/1203

Abstract: A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

Abstract translation: 用于SOI CMOS中的FET的器件设计，其被设计用于当FET导通时增强通过器件的电流的雪崩倍增，并且当FET关闭时去除体电荷。 FET具有电浮动体并且与衬底基本上电隔离。 本发明提供了将FET的浮体耦合到FET的源极的高电阻路径，使得该电阻器使得该器件能够充当用于有源开关目的的浮动体并且作为待机模式中的接地体以减少 漏电流。 高电阻路径具有至少1MΩ的电阻，并且包括通过使用分离多晶硅工艺制造的多晶硅电阻器，其中掩埋接触掩模在第一多晶硅层中打开孔，以允许第二多晶硅层 接触基板。

公开(公告)号：US5485095A

公开(公告)日：1996-01-16

申请号：US337342

申请日：1994-11-10

Applicant: John E. Bertsch ,  Randy W. Mann ,  Edward J. Nowak ,  Minh H. Tong

Inventor： John E. Bertsch ,  Randy W. Mann ,  Edward J. Nowak ,  Minh H. Tong

IPC: G01R31/28 ,  G01R31/02

CPC classification number: G01R31/2884

Abstract: Test circuits and methods for accurately flagging out-of-spec resistance in a current carrying structure of an integrated circuit employ a plurality of monitor structures connected in parallel and a test means for monitoring the monitor structures. Each monitor structure includes a test structure and an associated threshold sensitive device. Each test structure is predesigned relative to the current carrying structure of the integrated circuit such that an out-of-spec resistance in the test structure signals a possible out-of-spec resistance in the current carrying structure. The threshold sensitive device of each monitor structure outputs a fail signal when resistance of the associated test structure is above a predefined level. The fail signal is representative of an out-of-spec resistance in the associated test structure and flags possible out-of-spec resistance in the current carrying structure. The test means simultaneously monitors the plurality of monitor structures for a fail signal. An automated test device is also disclosed for providing a binary count representative of a total number of out-of-spec test structures.

Abstract translation: 用于在集成电路的载流结构中精确地标记超出规格电阻的测试电路和方法采用并联连接的多个监视器结构和用于监视监视器结构的测试装置。 每个监视器结构包括测试结构和相关联的阈值敏感设备。 每个测试结构相对于集成电路的电流承载结构是预先设计的，使得测试结构中的超出规格的电阻指示了当前承载结构中可能的超出规格的电阻。 当相关测试结构的电阻高于预定水平时，每个监视器结构的阈值敏感设备输出失败信号。 故障信号表示相关测试结构中超出规格的电阻，并标记了当前载波结构中可能超出规格的电阻。 测试装置同时监视多个监视器结构以用于失败信号。 还公开了一种自动测试装置，用于提供表示超出规格测试结构的总数的二进制计数。

公开(公告)号：US06528846B1

公开(公告)日：2003-03-04

申请号：US09404039

申请日：1999-09-23

Applicant: Edward J. Nowak ,  Minh H. Tong

Inventor： Edward J. Nowak ,  Minh H. Tong

IPC: H01L2976

CPC classification number: H01L29/66772 ,  H01L29/78624

Abstract: A silicon on insulation device having halo extensions of source and drain regions and an additional implant for inducing silicon lattice damage is able to withstand high operating voltages. A field lowering Lightly Doped Drain implant and removal of standard damaging source implants decreases avalanche currents and significantly increases drain-to-source breakdown voltage.

Abstract translation: 具有源极和漏极区域的光晕延伸的硅绝缘装置以及用于引起硅晶格损伤的附加植入物能够承受高的工作电压。 降低轻掺杂漏极注入和去除标准损伤源植入物的场减少雪崩电流并显着增加漏极到源极击穿电压。

公开(公告)号：US06437594B1

公开(公告)日：2002-08-20

申请号：US09528350

申请日：2000-03-17

Applicant: Ronald J. Bolam ,  Andres Bryant ,  Edward J. Nowak ,  Minh H. Tong

Inventor： Ronald J. Bolam ,  Andres Bryant ,  Edward J. Nowak ,  Minh H. Tong

IPC: G01R2722

CPC classification number: G01R31/3004

Abstract: A monitor for detecting pass gate leakage in a silicon on insulator device and a method for using the same is described herein. A pulse generator supplies a signal to a set of buffers connected in parallel, which pass on a signal to the source side of a series of NFETs. The plurality of NFETs are ordered by increasing channel widths. The NFETs have grounded gates, and therefore will not pass current due to field effects. Each NFET is connected to a latch, and the latches are originally set to the same state. When the signal supplied to the NFET drops from high to low, pass gate leakage will occur through the channel of each NFET. If pass gate leakage through any given NFET is sufficient, the latch will change states. The latch output signal is sent to a shift register, which can be made to output information. By incorporating the monitor on the chip, pass gate leakage tolerances and specifications can be established in-line during manufacture.

Abstract translation: 这里描述了一种用于检测绝缘体上硅器件中的漏极泄漏的监视器及其使用方法。 脉冲发生器将信号提供给并联连接的一组缓冲器，该缓冲器将信号传递到一系列NFET的源极侧。 通过增加通道宽度来排列多个NFET。 NFET具有接地栅极，因此由于场效应而不会通过电流。 每个NFET连接到一个锁存器，并且锁存器最初设置为相同的状态。 当提供给NFET的信号从高到低时，通过每个NFET的通道将发生栅极泄漏。 如果通过任何给定NFET的漏极泄漏就足够了，锁存器将改变状态。 锁存器输出信号发送到移位寄存器，可以输出信息。 通过将显示器结合在芯片上，可以在制造过程中在线建立传递门泄漏公差和规格。

公开(公告)号：US06200843B1

公开(公告)日：2001-03-13

申请号：US09159841

申请日：1998-09-24

Applicant: Andres Bryant ,  Edward J. Nowak ,  Minh H. Tong

Inventor： Andres Bryant ,  Edward J. Nowak ,  Minh H. Tong

IPC: H01L218238

CPC classification number: H01L29/42368 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/823857 ,  H01L27/092 ,  Y10S438/981

Abstract: A method for forming a semiconductor device. A substrate is provided. A first electrically insulating layer is formed on the substrate. A second electrically insulating layer is formed on the first electrically insulating layer. Openings are formed through the second electrically insulating layer down to the level of the first electrically insulating layer. Spacers are formed on opposing sidewalls of the openings. The spacers on one of the opposing side walls of the openings are removed, thereby exposing portions of the first electrically insulating layer. Exposed portions of the first electrically insulating layer in the openings are removed, thereby exposing portions of the substrate. The spacers on another of the opposing sidewalls of the openings are removed, thereby exposing portions of the first electrically insulating layer. A third electrically insulating layer is formed in the openings over the exposed portions of the first electrically insulating layer and the exposed portions of the substrate.

Abstract translation: 一种形成半导体器件的方法。 提供基板。 在基板上形成第一电绝缘层。 在第一电绝缘层上形成第二电绝缘层。 通过第二电绝缘层形成通向第一电绝缘层的水平面的开口。 间隔件形成在开口的相对侧壁上。 去除开口的一个相对侧壁上的间隔件，从而暴露第一电绝缘层的部分。 去除开口中的第一电绝缘层的暴露部分，从而暴露基板的部分。 去除开口的另一相对侧壁上的间隔物，从而暴露第一电绝缘层的部分。 在第一电绝缘层的暴露部分和基板的暴露部分的开口中形成第三电绝缘层。

公开(公告)号：US5528188A

公开(公告)日：1996-06-18

申请号：US402793

申请日：1995-03-13

Applicant: Wai-Ming W. Au ,  Minh H. Tong

Inventor： Wai-Ming W. Au ,  Minh H. Tong

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0259

Abstract: A resistance capacitance (RC) coupled low-voltage triggering silicon-controlled rectifier (LVTSCR) suppression circuit is presented for protecting an integrated circuit from electrostatic discharges or other potentially damaging voltage transients occurring at an input and/or output node of the integrated circuit or integrated circuit chip. The suppression circuit includes a discharge circuit and a trigger circuit. The discharge circuit is electrically coupled to the input and/or output node for dissipating the electrostatic discharge, while the trigger circuit is electrically connected to the input and/or output node and to the discharge circuit. The trigger circuit provides direct low-voltage turn-on of the discharge circuit as the electrostatic discharge builds at the input and/or output node of the integrated circuit. The trigger circuit includes a transistor having a control gate, and an RC circuit connected to the control gate and to the input and/or output node such that the control gate is electrically coupled to the input and/or output node across a capacitance and to ground across a resistance.

Abstract translation: 提出了耦合低电压触发硅控整流器（LVTSCR）抑制电路的电阻电容（RC），用于保护集成电路免受在集成电路的输入和/或输出节点处发生的静电放电或其他潜在的破坏性电压瞬变，或 集成电路芯片。 抑制电路包括放电电路和触发电路。 放电电路电耦合到输入和/或输出节点，用于消散静电放电，而触发电路电连接到输入和/或输出节点和放电电路。 当集成电路的输入和/或输出节点处建立静电放电时，触发电路提供放电电路的直接低电压接通。 触发电路包括具有控制栅极的晶体管和连接到控制栅极和输入和/或输出节点的RC电路，使得控制栅极跨过电容电耦合到输入和/或输出节点，并且 穿越阻力。

公开(公告)号：US4811298A

公开(公告)日：1989-03-07

申请号：US87489

申请日：1987-08-20

Applicant: Klaus Helwig ,  Wolfdieter Lohlein ,  Minh H. Tong

Inventor： Klaus Helwig ,  Wolfdieter Lohlein ,  Minh H. Tong

IPC: G11C11/408 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC classification number: G11C29/83 ,  G11C29/84

Abstract: A decoding process and a decoding circuit arrangement for a redundant semiconductor memory is described, wherein the advantages of parallelly selecting non-defective word lines and redundant word lines at a low level are utilized for the writing as well as for the reading current in such a manner that high speed reading and writing is not affected. This is achieved in that the decoder for the redundant word lines consists of a comparator circuit and fuse-controlled switches, and that the input addresses are applied to a conventional address decoder as well as to the comparator circuit. The output of the comparator circuit is directly connected to the input of a first driver circuit for the redundant word line, and furthermore to an OR circuit which is also controlled by a read/write control circuit, and which is connected to the decoder and to a clamp circuit that is directly connected to the input of a second word line driver circuit, and continuously maintains the potential following a deselect signal applied on that level, which requires a minimum of power.

Abstract translation: 描述了用于冗余半导体存储器的解码处理和解码电路装置，其中以低电平并行选择无缺陷字线和冗余字线的优点用于写入以及读取电流 高速读写方式不受影响。 这是因为用于冗余字线的解码器由比较器电路和熔丝控制开关组成，并且输入地址被施加到常规地址解码器以及比较器电路。 比较器电路的输出直接连接到用于冗余字线的第一驱动器电路的输入，并且还连接到也由读/写控制电路控制并且连接到解码器的OR电路， 钳位电路，其直接连接到第二字线驱动器电路的输入，并且连续地保持该电平上施加的取消选择信号的电位，其需要最小功率。

公开(公告)号：US06838323B2

公开(公告)日：2005-01-04

申请号：US10341182

申请日：2003-01-13

Applicant: Robert J. Gauthier ,  Edward J. Nowak ,  Xiaowei Tian ,  Minh H. Tong ,  Steven H. Voldman

Inventor： Robert J. Gauthier ,  Edward J. Nowak ,  Xiaowei Tian ,  Minh H. Tong ,  Steven H. Voldman

IPC: H01L27/02 ,  H01L21/00 ,  H01L23/62

CPC classification number: H01L27/0288 ,  H01L27/0251 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and process for making a non-aligned MOSFET structure for ESD protection using resistor wells as the diffusions and adjustable capacitors. The present invention compensates the shallow extension region without the need for additional masks. The source/drain doping is less than that of a normal MOSFET but extends deeper into the silicon since the present invention uses a resistor well as the source/drain. The deeper emitter/collector increases the second trigger current of the NFET when used as an ESD protection device.

Abstract translation: 使用电阻阱作为扩散和可调电容器制造用于ESD保护的非对准MOSFET结构的结构和工艺。 本发明补偿了浅扩展区域，而不需要额外的掩模。 源极/漏极掺杂小于普通MOSFET的源极/漏极掺杂，但是由于本发明使用电阻阱作为源极/漏极，因此更深地延伸到硅中。 当用作ESD保护器件时，较深的发射极/集电极增加了NFET的第二个触发电流。