公开(公告)号：US20080272373A1

公开(公告)日：2008-11-06

申请号：US12172321

申请日：2008-07-14

申请人： Ki Hong Yang ,  Sang Wook Park

发明人： Ki Hong Yang ,  Sang Wook Park

IPC分类号： H01L29/788

CPC分类号： H01L27/11541 ,  H01L27/105 ,  H01L27/11526

摘要： A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the resistivity of the floating gate to be measured even in the SAFG scheme. Contacts for resistivity measurement are directly connected to the resistivity measurement floating gate. Therefore, variation in resistivity measurement values, which is incurred by the parasitic interface, can be reduced.

摘要翻译： 闪速存储器件具有电阻率测量图案及其形成方法。 在自对准浮动门（SAFG）方案中的隔离膜中形成沟槽。 埋入沟槽以形成电阻率测量浮栅。 这允许甚至在SAFG方案中测量浮动栅极的电阻率。 用于电阻率测量的触点直接连接到电阻率测量浮栅。 因此，可以减少由寄生接口引起的电阻率测量值的变化。

公开(公告)号：US07829934B2

公开(公告)日：2010-11-09

申请号：US12172321

申请日：2008-07-14

申请人： Ki Hong Yang ,  Sang Wook Park

发明人： Ki Hong Yang ,  Sang Wook Park

IPC分类号： H01L29/66

CPC分类号： H01L27/11541 ,  H01L27/105 ,  H01L27/11526

摘要： A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the resistivity of the floating gate to be measured even in the SAFG scheme. Contacts for resistivity measurement are directly connected to the resistivity measurement floating gate. Therefore, variation in resistivity measurement values, which is incurred by the parasitic interface, can be reduced.

摘要翻译： 闪速存储器件具有电阻率测量图案及其形成方法。 在自对准浮动门（SAFG）方案中的隔离膜中形成沟槽。 埋入沟槽以形成电阻率测量浮栅。 这允许甚至在SAFG方案中测量浮动栅极的电阻率。 用于电阻率测量的触点直接连接到电阻率测量浮栅。 因此，可以减少由寄生接口引起的电阻率测量值的变化。

公开(公告)号：US07439131B2

公开(公告)日：2008-10-21

申请号：US11164677

申请日：2005-12-01

申请人： Ki Hong Yang ,  Sang Wook Park

发明人： Ki Hong Yang ,  Sang Wook Park

IPC分类号： H01L21/336

CPC分类号： H01L27/11541 ,  H01L27/105 ,  H01L27/11526

摘要： A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the resistivity of the floating gate to be measured even in the SAFG scheme. Contacts for resistivity measurement are directly connected to the resistivity measurement floating gate. Therefore, variation in resistivity measurement values, which is incurred by the parasitic interface, can be reduced.

摘要翻译： 闪速存储器件具有电阻率测量图案及其形成方法。 在自对准浮动门（SAFG）方案中的隔离膜中形成沟槽。 埋入沟槽以形成电阻率测量浮栅。 这允许甚至在SAFG方案中测量浮动栅极的电阻率。 用于电阻率测量的触点直接连接到电阻率测量浮栅。 因此，可以减少由寄生接口引起的电阻率测量值的变化。

公开(公告)号：US07479453B2

公开(公告)日：2009-01-20

申请号：US11159306

申请日：2005-06-23

申请人： Jung Geun Kim ,  Ki Hong Yang

发明人： Jung Geun Kim ,  Ki Hong Yang

IPC分类号： H01L21/44

CPC分类号： H01L21/321 ,  H01L21/02252 ,  H01L21/0234 ,  H01L21/2855 ,  H01L21/3105 ,  H01L21/31608 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76838 ,  H01L21/76886

摘要： A method of manufacturing a semiconductor device in a MLM process to reduce compression stress of a metal line or a HDP oxide film, and to reduce compression stress in a subsequent metal line thermal treatment process. It is thus possible to reduce generation of a crack caused by compression stress. Further, by obviating a heterogeneous interface becoming a cause of a crack and stabilizing the interface of an unstable TEOS oxide film, generation of a crack in a semiconductor device can be reduced.

摘要翻译： 一种在MLM工艺中制造半导体器件以降低金属线或HDP氧化物膜的压缩应力的方法，并且在随后的金属线热处理工艺中降低压缩应力。 因此，可以减少由压缩应力引起的裂纹的产生。 此外，通过消除异质界面成为裂纹的原因并稳定不稳定的TEOS氧化物膜的界面，可以减少半导体器件中的裂纹的产生。