公开(公告)号：US08685627B2

公开(公告)日：2014-04-01

申请号：US12266459

申请日：2008-11-06

申请人： Ki Lyoung Lee ,  Cheol Kyu Bok ,  Keum Do Ban ,  Jung Gun Heo

发明人： Ki Lyoung Lee ,  Cheol Kyu Bok ,  Keum Do Ban ,  Jung Gun Heo

IPC分类号： H01L21/02

CPC分类号： H01L21/308 ,  H01L21/0337

摘要： A method for manufacturing a semiconductor device includes forming an etch-target layer over a semiconductor substrate having a lower structure, forming a first mask pattern over the etch-target layer, forming a spacer material layer with a uniform thickness over the etch-target layer including the first mask pattern, forming a second mask pattern on an indented region of the space material layer, and etching the etch-target layer with the first mask pattern and the second mask pattern as an etch mask to form a fine pattern.

摘要翻译： 一种用于制造半导体器件的方法包括在具有较低结构的半导体衬底上形成蚀刻目标层，在蚀刻靶层上形成第一掩模图案，在蚀刻靶层上形成均匀厚度的间隔物材料层 包括第一掩模图案，在空间材料层的凹陷区域上形成第二掩模图案，并且用第一掩模图案和第二掩模图案蚀刻蚀刻目标层作为蚀刻掩模以形成精细图案。

公开(公告)号：US07994050B2

公开(公告)日：2011-08-09

申请号：US12804150

申请日：2010-07-15

申请人： Ki Lyoung Lee ,  Jung Gun Heo

发明人： Ki Lyoung Lee ,  Jung Gun Heo

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/31144

摘要： A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin, wherein the silicon resin comprises about 20 to 45% silicon molecules by weight, based on a total weight of the resin; forming a deposition structure by sequentially forming a self-arrangement contact (SAC) insulating film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; coating the multi-functional hard mask composition over the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film using a photoresist pattern as an etching mask, thereby forming a trench having a width greater than that of the via hole.

摘要翻译： 形成双镶嵌图案的方法包括制备包括硅树脂作为基础树脂的多功能硬掩模组合物，其中所述硅树脂占树脂总重量的约20至45重量％的硅分子; 通过在硬接线层上依次形成自配置接触（SAC）绝缘膜，第一电介质膜，蚀刻阻挡膜和第二电介质膜来形成沉积结构; 蚀刻沉积结构以暴露硬接线层，从而形成通孔; 在第二电介质膜上和通孔中涂覆多功能硬掩模组合物以形成多功能硬掩模膜; 并蚀刻所得到的结构，以使用光致抗蚀剂图案作为蚀刻掩模使第一电介质膜的一部分露出，从而形成宽度大于通孔的宽度的沟槽。

公开(公告)号：US20100311239A1

公开(公告)日：2010-12-09

申请号：US12804150

申请日：2010-07-15

申请人： Ki Lyoung Lee ,  Jung Gun Heo

发明人： Ki Lyoung Lee ,  Jung Gun Heo

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/31144

摘要： A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin, wherein the silicon resin comprises about 20 to 45% silicon molecules by weight, based on a total weight of the resin; forming a deposition structure by sequentially forming a self-arrangement contact (SAC) insulating film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; coating the multi-functional hard mask composition over the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film using a photoresist pattern as an etching mask, thereby forming a trench having a width greater than that of the via hole.

摘要翻译： 形成双镶嵌图案的方法包括制备包括硅树脂作为基础树脂的多功能硬掩模组合物，其中所述硅树脂占树脂总重量的约20至45重量％的硅分子; 通过在硬接线层上依次形成自配置接触（SAC）绝缘膜，第一电介质膜，蚀刻阻挡膜和第二电介质膜来形成沉积结构; 蚀刻沉积结构以暴露硬接线层，从而形成通孔; 在第二电介质膜上和通孔中涂覆多功能硬掩模组合物以形成多功能硬掩模膜; 并蚀刻所得到的结构，以使用光致抗蚀剂图案作为蚀刻掩模使第一电介质膜的一部分露出，从而形成宽度大于通孔的宽度的沟槽。

公开(公告)号：US07811929B2

公开(公告)日：2010-10-12

申请号：US11812910

申请日：2007-06-22

申请人： Ki Lyoung Lee ,  Jung Gun Heo

发明人： Ki Lyoung Lee ,  Jung Gun Heo

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/31144

摘要： A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin; forming a deposition structure including a self-arrangement contact insulation film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; forming the multi-functional hard mask composition on the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film, thereby forming a trench having a width wider than that of the via hole; and removing the multi-functional hard mask film.

摘要翻译： 形成双镶嵌图案的方法包括制备包括硅树脂作为基础树脂的多功能硬掩模组合物; 在硬接线层上形成包括自配置接触绝缘膜，第一电介质膜，蚀刻阻挡膜和第二电介质膜的沉积结构; 蚀刻沉积结构以暴露硬接线层，从而形成通孔; 在第二电介质膜和通孔中形成多功能硬掩模组合物以形成多功能硬掩模膜; 并蚀刻所得到的结构以暴露第一电介质膜的一部分，从而形成宽度大于通孔的宽度的沟槽; 并去除多功能硬掩模膜。

公开(公告)号：US20080268641A1

公开(公告)日：2008-10-30

申请号：US11812910

申请日：2007-06-22

申请人： Ki Lyoung Lee ,  Jung Gun Heo

发明人： Ki Lyoung Lee ,  Jung Gun Heo

IPC分类号： H01L21/768 ,  H01L21/3065

CPC分类号： H01L21/76808 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/31144

摘要： A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin; forming a deposition. structure including a self-arrangement contact insulation film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; forming the multi-functional hard mask composition on the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film, thereby forming a trench having a width wider than that of the via hole; and removing the multi-functional hard mask film.

摘要翻译： 形成双镶嵌图案的方法包括制备包括硅树脂作为基础树脂的多功能硬掩模组合物; 形成沉积物。 包括自配置接触绝缘膜，第一电介质膜，蚀刻阻挡膜和在硬接线层上的第二电介质膜的结构; 蚀刻沉积结构以暴露硬接线层，从而形成通孔; 在第二电介质膜和通孔中形成多功能硬掩模组合物以形成多功能硬掩模膜; 并蚀刻所得到的结构以暴露第一电介质膜的一部分，从而形成宽度大于通孔的宽度的沟槽; 并去除多功能硬掩模膜。

公开(公告)号：US07964510B2

公开(公告)日：2011-06-21

申请号：US12345378

申请日：2008-12-29

申请人： Jung Gun Heo

发明人： Jung Gun Heo

IPC分类号： H01L21/302

CPC分类号： H01L21/0337 ,  Y10S438/947 ,  Y10S438/95

摘要： A method for forming a pattern of a semiconductor device includes: forming a first mask film and a second mask film over an underlying layer; partially etching the first and second mask films using a photoresist mask pattern as an etching mask to form a intermediate mask pattern having a protrusion shape and including first and second mask film layers, over a remaining portion of the first mask film; forming a first spacer at sidewalls of the intermediate mask pattern etching the remaining portion of the first mask film and the first mask film layer of the intermediate mask pattern using the first spacer and the second mask film layer of the intermediate mask pattern as an etching mask to expose the underlying layer and form a mask pattern having first and second mask film layers; forming a second spacer at sidewalls of the mask pattern; and removing the mask pattern to form a symmetrical spacer pattern.

摘要翻译： 用于形成半导体器件的图案的方法包括：在下层上形成第一掩模膜和第二掩模膜; 使用光致抗蚀剂掩模图案作为蚀刻掩模来部分地蚀刻第一和第二掩模膜，以在第一掩模膜的剩余部分上形成具有突起形状并包括第一和第二掩模膜层的中间掩模图案; 在中间掩模图案的侧壁处形成第一间隔物，使用第一间隔物和中间掩模图案的第二掩模膜层作为蚀刻掩模蚀刻第一掩模膜的剩余部分和中间掩模图案的第一掩模膜层 露出下层并形成具有第一和第二掩模膜层的掩模图案; 在所述掩模图案的侧壁处形成第二间隔物; 并去除掩模图案以形成对称的间隔图案。

公开(公告)号：US20090246961A1

公开(公告)日：2009-10-01

申请号：US12345378

申请日：2008-12-29

申请人： Jung Gun Heo

发明人： Jung Gun Heo

IPC分类号： H01L21/71

CPC分类号： H01L21/0337 ,  Y10S438/947 ,  Y10S438/95

摘要： A method for forming a pattern of a semiconductor device includes: forming a first mask film and a second mask film over an underlying layer; partially etching the first and second mask films using a photoresist mask pattern as an etching mask to form a intermediate mask pattern having a protrusion shape and including first and second mask film layers, over a remaining portion of the first mask film; forming a first spacer at sidewalls of the intermediate mask pattern etching the remaining portion of the first mask film and the first mask film layer of the intermediate mask pattern using the first spacer and the second mask film layer of the intermediate mask pattern as an etching mask to expose the underlying layer and form a mask pattern having first and second mask film layers; forming a second spacer at sidewalls of the mask pattern; and removing the mask pattern to form a symmetrical spacer pattern.

摘要翻译： 用于形成半导体器件的图案的方法包括：在下层上形成第一掩模膜和第二掩模膜; 使用光致抗蚀剂掩模图案作为蚀刻掩模来部分地蚀刻第一和第二掩模膜，以在第一掩模膜的剩余部分上形成具有突起形状并包括第一和第二掩模膜层的中间掩模图案; 在中间掩模图案的侧壁处形成第一间隔物，使用第一间隔物和中间掩模图案的第二掩模膜层作为蚀刻掩模蚀刻第一掩模膜的剩余部分和中间掩模图案的第一掩模膜层 露出下层并形成具有第一和第二掩模膜层的掩模图案; 在所述掩模图案的侧壁处形成第二间隔物; 并去除掩模图案以形成对称的间隔图案。