公开(公告)号：US20080188057A1

公开(公告)日：2008-08-07

申请号：US12070808

申请日：2008-02-21

申请人： Ki-Seog Youn ,  Jong-Hyon Ahn ,  Deok-Hyung Lee ,  Sung-Gun Kang ,  Kong-Soo Cheong

发明人： Ki-Seog Youn ,  Jong-Hyon Ahn ,  Deok-Hyung Lee ,  Sung-Gun Kang ,  Kong-Soo Cheong

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.

摘要翻译： 提供其中防止在场区域中形成凹部的沟槽隔离型半导体器件及其制造方法。 沟槽隔离型半导体器件包括由有源区和场区定义的半导体衬底，在场区中形成的沟槽，沿着沟内部保形地形成的氧化物层，沿着氧化物层保形地形成的衬层， 形成在包括氧化物层和衬垫层的沟槽内的场绝缘层，以及形成在场绝缘层上的场保护层，使得半导体衬底上不发生阶差。

公开(公告)号：US07094694B2

公开(公告)日：2006-08-22

申请号：US11023623

申请日：2004-12-29

申请人： Kong-Soo Cheong ,  Ki-Seog Youn ,  Kyung-Soo Kim

发明人： Kong-Soo Cheong ,  Ki-Seog Youn ,  Kyung-Soo Kim

IPC分类号： H01L21/44

CPC分类号： H01L29/6659 ,  H01L27/0629 ,  H01L29/665 ,  H01L29/6656

摘要： In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in a second region. A lightly doped source/drain region is formed on surface of the first region. A second gate spacer is formed on sidewalls of the first gate spacer. A heavily doped source/drain region is formed on the surface of the first region. A silicide layer is formed on the gate electrode and the heavily doped source/drain region in the first region.

摘要翻译： 在制造半导体器件的方法中，栅电极形成在第一区域中。 图案化硅化物阻挡层，使得第一栅极间隔物形成在栅电极的侧壁上，并且在第二区域中形成硅化物阻挡层图案。 在第一区域的表面上形成轻掺杂的源极/漏极区域。 在第一栅极间隔物的侧壁上形成第二栅极间隔物。 在第一区域的表面上形成重掺杂的源极/漏极区域。 在栅电极和第一区域中的重掺杂源极/漏极区域上形成硅化物层。

公开(公告)号：US07361565B2

公开(公告)日：2008-04-22

申请号：US11037506

申请日：2005-01-18

申请人： Jeong-Ho Shin ,  Jong-Hyon Ahn ,  Kong-Soo Cheong ,  Jin-Won Jun

发明人： Jeong-Ho Shin ,  Jong-Hyon Ahn ,  Kong-Soo Cheong ,  Jin-Won Jun

IPC分类号： H01L21/336

CPC分类号： H01L29/66553 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.

摘要翻译： 在半导体器件中形成金属栅极的方法中，在衬底上形成栅极绝缘图案和伪栅极图案。 在伪栅极图案上形成绝缘中间层以覆盖伪栅极图案。 抛光绝缘夹层，使得裸露栅极图案的顶表面露出，并且选择性地去除伪栅极图案以在衬底上形成沟槽。 栅极间隔件形成在沟槽的内侧壁上，用于确定金属栅极的栅极长度。 将金属沉积到足够的厚度以填充沟槽以形成金属层。 金属层被抛光以保留在沟槽中。 因此，金属栅极的栅极长度可以减小到不超过光刻曝光系统的分辨率极限。

公开(公告)号：US20050142779A1

公开(公告)日：2005-06-30

申请号：US11023623

申请日：2004-12-29

申请人： Kong-Soo Cheong ,  Ki-Seog Youn ,  Kyung-Soo Kim

发明人： Kong-Soo Cheong ,  Ki-Seog Youn ,  Kyung-Soo Kim

IPC分类号： H01L21/336 ,  H01L27/06

CPC分类号： H01L29/6659 ,  H01L27/0629 ,  H01L29/665 ,  H01L29/6656

摘要： In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in a second region. A lightly doped source/drain region is formed on surface of the first region. A second gate spacer is formed on sidewalls of the first gate spacer. A heavily doped source/drain region is formed on the surface of the first region. A silicide layer is formed on the gate electrode and the heavily doped source/drain region in the first region.

摘要翻译： 在制造半导体器件的方法中，栅电极形成在第一区域中。 图案化硅化物阻挡层，使得第一栅极间隔物形成在栅电极的侧壁上，并且在第二区域中形成硅化物阻挡层图案。 在第一区域的表面上形成轻掺杂的源极/漏极区域。 在第一栅极间隔物的侧壁上形成第二栅极间隔物。 在第一区域的表面上形成重掺杂的源极/漏极区域。 在栅电极和第一区域中的重掺杂源极/漏极区域上形成硅化物层。

公开(公告)号：US20050158935A1

公开(公告)日：2005-07-21

申请号：US11037506

申请日：2005-01-18

申请人： Jeong-Ho Shin ,  Jong-Hyon Ahn ,  Kong-Soo Cheong ,  Jin-Won Jun

发明人： Jeong-Ho Shin ,  Jong-Hyon Ahn ,  Kong-Soo Cheong ,  Jin-Won Jun

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66553 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.

摘要翻译： 在半导体器件中形成金属栅极的方法中，在衬底上形成栅极绝缘图案和伪栅极图案。 在伪栅极图案上形成绝缘中间层以覆盖伪栅极图案。 抛光绝缘夹层，使得裸露栅极图案的顶表面露出，并且选择性地去除伪栅极图案以在衬底上形成沟槽。 栅极间隔件形成在沟槽的内侧壁上，用于确定金属栅极的栅极长度。 将金属沉积到足够的厚度以填充沟槽以形成金属层。 金属层被抛光以保留在沟槽中。 因此，金属栅极的栅极长度可以减小到不超过光刻曝光系统的分辨率极限。

公开(公告)号：US07485558B2

公开(公告)日：2009-02-03

申请号：US11041555

申请日：2005-01-24

申请人： Sung-Gun Kang ,  Kong-Soo Cheong ,  Jeong-Ho Shin ,  Ki-Young Kim

发明人： Sung-Gun Kang ,  Kong-Soo Cheong ,  Jeong-Ho Shin ,  Ki-Young Kim

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/823807 ,  H01L21/28518 ,  H01L21/823814

摘要： In a method of manufacturing a semiconductor device, a preliminary metal silicide layer is selectively formed on a substrate having a transistor, the transistor having source/drain regions. A capping layer having a thermal expansion coefficient greater than that of the preliminary metal silicide layer is formed on the substrate having the preliminary metal silicide layer. The substrate is thermally treated to form a metal silicide layer, and to apply a tensile stress caused by a thermal expansion coefficient difference between the metal silicide layer and the capping layer to the source/drain regions of the transistor.

摘要翻译： 在制造半导体器件的方法中，在具有晶体管的衬底上选择性地形成预备金属硅化物层，该晶体管具有源极/漏极区域。 在具有预备金属硅化物层的基板上形成热膨胀系数大于初始金属硅化物层的热膨胀系数的覆盖层。 将基板热处理以形成金属硅化物层，并将由金属硅化物层和封盖层之间的热膨胀系数差导致的拉伸应力施加到晶体管的源极/漏极区域。

公开(公告)号：US20050164437A1

公开(公告)日：2005-07-28

申请号：US11041555

申请日：2005-01-24

申请人： Sung-Gun Kang ,  Kong-Soo Cheong ,  Jeong-Ho Shin ,  Ki-Young Kim

发明人： Sung-Gun Kang ,  Kong-Soo Cheong ,  Jeong-Ho Shin ,  Ki-Young Kim

IPC分类号： H01L21/285 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/28518 ,  H01L21/823814

摘要： In a method of manufacturing a semiconductor device, a preliminary metal silicide layer is selectively formed on a substrate having a transistor, the transistor having source/drain regions. A capping layer having a thermal expansion coefficient greater than that of the preliminary metal silicide layer is formed on the substrate having the preliminary metal silicide layer. The substrate is thermally treated to form a metal silicide layer, and to apply a tensile stress caused by a thermal expansion coefficient difference between the metal silicide layer and the capping layer to the source/drain regions of the transistor.

摘要翻译： 在制造半导体器件的方法中，在具有晶体管的衬底上选择性地形成预备金属硅化物层，该晶体管具有源极/漏极区域。 在具有预备金属硅化物层的基板上形成热膨胀系数大于初始金属硅化物层的热膨胀系数的覆盖层。 将基板热处理以形成金属硅化物层，并将由金属硅化物层和封盖层之间的热膨胀系数差导致的拉伸应力施加到晶体管的源极/漏极区域。

公开(公告)号：US06812111B2

公开(公告)日：2004-11-02

申请号：US10292340

申请日：2002-11-12

申请人： Kong-Soo Cheong ,  Hee-Sung Kang

发明人： Kong-Soo Cheong ,  Hee-Sung Kang

IPC分类号： H01L2120

CPC分类号： H01L29/66583 ,  H01L21/28114 ,  H01L21/28238 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7833

摘要： In methods for fabricating MOS transistors with notched gate electrodes, a notched gate electrode may be readily fabricated using a damascene process for filling a stair-shaped opening formed in a multi-layered insulation layer. In this manner, the width and a height of the notch region of the gate electrode may be readily adjusted and controlled.

摘要翻译： 在用于制造具有带槽栅电极的MOS晶体管的方法中，可以使用用于填充形成在多层绝缘层中的阶梯形开口的镶嵌工艺来容易地制造缺口栅电极。 以这种方式，可以容易地调节和控制栅电极的切口区域的宽度和高度。