公开(公告)号：US6127197A

公开(公告)日：2000-10-03

申请号：US104716

申请日：1998-06-25

申请人： Kil Ho Kim ,  Kang Sup Shin ,  Jong Il Kim

发明人： Kil Ho Kim ,  Kang Sup Shin ,  Jong Il Kim

IPC分类号： G01B7/02 ,  G01B21/02 ,  H01L21/66

CPC分类号： G01B7/02

摘要： In order to measure a width of a wire a measuring pattern for the width of the wire is prepared. The measuring pattern includes: a first pattern with a first width; a second pattern connected to the first pattern and having a second width wider than the first width; and a third pattern connected to the second pattern and having a third width narrower than the first width. The first pattern, the second pattern and the third pattern are made of same material. The first pattern through a power source is connected to the third pattern. A first pair of probes are disposed on the first pattern and then are connected to a first voltmeter. A distance between the first pair of probes is a first distance wider than the first width. A second pair of probes are disposed on the second pattern and then are connected to a second voltmeter. A distance between the second pair of probes is a second distance wider than the first width. Thereafter the first width using gauged voltage at the first voltmeter and the second voltmeter is determined. The second width is more substantially ten times the first width and the third width is such narrow that current therethrough is uniform.

摘要翻译： 为了测量线的宽度，准备线的宽度的测量图案。 测量图案包括：具有第一宽度的第一图案; 连接到第一图案并且具有比第一宽度宽的第二宽度的第二图案; 以及连接到第二图案并且具有比第一宽度窄的第三宽度的第三图案。 第一图案，第二图案和第三图案由相同的材料制成。 通过电源的第一模式连接到第三模式。 第一对探针设置在第一图案上，然后连接到第一电压表。 第一对探针之间的距离是比第一宽度宽的第一距离。 第二对探针设置在第二图案上，然后连接到第二电压表。 第二对探针之间的距离是比第一宽度宽的第二距离。 此后，确定在第一电压表和第二电压表下使用测量电压的第一宽度。 第二宽度基本上是第一宽度的十倍，并且第三宽度使得通过其中的电流是均匀的。

公开(公告)号：US06462565B1

公开(公告)日：2002-10-08

申请号：US09644992

申请日：2000-08-24

申请人： Kil Ho Kim ,  Kang Sup Shin ,  Jong Il Kim

发明人： Kil Ho Kim ,  Kang Sup Shin ,  Jong Il Kim

IPC分类号： G01R2714

CPC分类号： G01B7/02

摘要： In order to measure a width of a wire a measuring pattern for the width of the wire is prepared. The measuring pattern includes: a first pattern with a first width; a second pattern connected to the first pattern and having a second width wider than the first width; and a third pattern connected to the second pattern and having a third width narrower than the first width. The first pattern, the second pattern and the third pattern are made of same material. The first pattern through a power source is connected to the third pattern. A first pair of probes are disposed on the first pattern and then are connected to a first voltmeter. A distance between the first pair of probes is a first distance wider than the first width. A second pair of probes are disposed on the second pattern and then are connected to a second voltmeter. A distance between the second pair of probes is a second distance wider than the first width. Thereafter the first width using gauged voltage at the first voltmeter and the second voltmeter is determined. The second width is more substantially ten times the first width and the third width is such narrow that current therethrough is uniform.

摘要翻译： 为了测量线的宽度，准备线的宽度的测量图案。 测量图案包括：具有第一宽度的第一图案; 连接到第一图案并且具有比第一宽度宽的第二宽度的第二图案; 以及连接到第二图案并且具有比第一宽度窄的第三宽度的第三图案。 第一图案，第二图案和第三图案由相同的材料制成。 通过电源的第一模式连接到第三模式。 第一对探针设置在第一图案上，然后连接到第一电压表。 第一对探针之间的距离是比第一宽度宽的第一距离。 第二对探针设置在第二图案上，然后连接到第二电压表。 第二对探针之间的距离是比第一宽度宽的第二距离。 此后，确定在第一电压表和第二电压表下使用测量电压的第一宽度。 第二宽度基本上是第一宽度的十倍，并且第三宽度使得通过其中的电流是均匀的。

公开(公告)号：US07160810B2

公开(公告)日：2007-01-09

申请号：US10878317

申请日：2004-06-29

申请人： Kang Sup Shin ,  Sang Wook Ryu

发明人： Kang Sup Shin ,  Sang Wook Ryu

IPC分类号： H01L21/311

CPC分类号： H01L21/76831 ,  H01L21/31116 ,  H01L21/76807

摘要： The present invention discloses a method for forming an interlayer insulation film in a semiconductor device, comprising the steps of: sequentially forming a porous low dielectric insulation film and a capping layer on the semiconductor substrate on which a few elements of the semiconductor device have been formed; and forming damascene patterns in the porous low dielectric insulation film by an etching process, and forming a protection film for closing pores exposed during the etching process at the same time.

摘要翻译： 本发明公开了一种在半导体器件中形成层间绝缘膜的方法，包括以下步骤：在半导体衬底上依次形成多孔低介电绝缘膜和覆盖层，半导体衬底上形成有半导体器件的几个元件 ; 并通过蚀刻工艺在多孔低介电绝缘膜中形成镶嵌图案，并且同时形成用于封闭在蚀刻工艺期间暴露的孔的保护膜。