公开(公告)号：US20210089393A1

公开(公告)日：2021-03-25

申请号：US16816396

申请日：2020-03-12

Applicant: Kioxia Corporation

Inventor： Naoaki KOKUBUN ,  Daiki WATANABE

IPC: G06F11/10 ,  H03M13/45

Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The memory controller converts a received value read from the nonvolatile memory into first likelihood information by using a first conversion table, executes decoding on the first likelihood information and outputting a posterior value, outputs an estimated value of the received value obtained on the basis of the posterior value in a case where the decoding is successful. The memory controller generates a second conversion table on the basis of the posterior value in a case where the decoding fails. The memory controller converts the received value into second likelihood information by using the second conversion table in a case where the second conversion table has been generated, and executes decoding on the second likelihood information and outputs a posterior value.

公开(公告)号：US20230305898A1

公开(公告)日：2023-09-28

申请号：US17897095

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Daiki WATANABE ,  Kenji SHIRAKAWA ,  Takeshi ISHIHARA

IPC: G06F9/50

CPC classification number: G06F9/5038

Abstract: In a resource allocation control device, a dependency information acquisition unit acquires dependency information indicating subdivided process items that constitute a task and a dependency of the process items. A resource information acquisition unit acquires resource information that is information indicating what kind of resource allocation is possible for the task. A score calculation unit calculates a score for a processing procedure of the process items based on the dependency information, and the resource allocation. A search unit searches for a combination of which the score is excellent. An output unit outputs resource allocation corresponding to the excellent score found by the search unit.

公开(公告)号：US20240311372A1

公开(公告)日：2024-09-19

申请号：US18592093

申请日：2024-02-29

Applicant: Kioxia Corporation

Inventor： Daiki WATANABE ,  Takeshi ISHIHARA ,  Kenji SHIRAKAWA

IPC: G06F16/2452 ,  G06F11/34 ,  G06F16/2453

CPC classification number: G06F16/24526 ,  G06F11/3409 ,  G06F16/24542

Abstract: A method for executing query processing includes, in response to a query from a host, generating a task graph indicating a plurality of task sequences, each of the task sequences capable f performing query processing corresponding to the query. The sequences includes a first sequence that outputs data in a first compression state to a one of output targets, and a second sequence of tasks that outputs the data in a second compression state different from the first compression state to the one of the output targets. The method further includes determining a processing cost for each of the task sequences, selecting one of the task sequences in accordance with the determined processing cost, and performing the query processing corresponding to the query in accordance with the selected task sequence.

公开(公告)号：US20220261312A1

公开(公告)日：2022-08-18

申请号：US17412026

申请日：2021-08-25

Applicant: Kioxia Corporation

Inventor： Takahiro KUBOTA ,  Daiki WATANABE ,  Hironori UCHIKAWA

IPC: G06F11/10

Abstract: A memory system includes a non-volatile memory configured to store an N-dimensional error correction code and a memory controller. The memory controller is configured to calculate an ath soft-input value for an ath component code based on correction information of the ath component code (1≤a≤ni) of an ith dimension (1≤i≤N), ath reliability information, and a syndrome value of the ath component code, to calculate a decoded word of the ath component code, the ath correction information, and the ath reliability information by inputting the ath soft-input value and executing a decoding process of the ath component code, to store the ath correction information and bth correction information indicating a corrected position of a bth component code (1≤b≤nj) of a jth dimension (j≠i, 1≤j≤N) in a correction information memory, to store the ath reliability information in a reliability information memory, and to output an output decoded word calculated from the read information and the reliability information of each component code.

公开(公告)号：US20210058097A1

公开(公告)日：2021-02-25

申请号：US16795657

申请日：2020-02-20

Applicant: Kioxia Corporation

Inventor： Daiki WATANABE

IPC: H03M13/29 ,  H03M13/15 ,  G06F11/10

Abstract: A memory system of an embodiment includes a non-volatile memory and a memory controller. The memory controller generates an error correction code including a first and second symbol groups. The first symbol group is a set of symbols shared between a first component code and a third component code and/or a fourth component code. The second symbol group is a set of symbols shared between a second component code and the third component code and/or the fourth component code. The first and third component codes have a lower correction capability than the second and fourth component codes, respectively. The ratio of symbols protected by the third component code is smaller in the second symbol group than in the first symbol group. The ratio of symbols protected by the fourth component code is larger in the second symbol group than in the first symbol group.