公开(公告)号：US12041772B2

公开(公告)日：2024-07-16

申请号：US17446106

申请日：2021-08-26

申请人： Kioxia Corporation

发明人： Hanae Ishihara

IPC分类号： H01L29/76 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC分类号： H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B43/27

摘要： A device includes a first region including first semiconductor pillars extending through first conductive layers; a second region including second semiconductor pillars extending through second conductive layers; and a third region disposed between the first region and the second region and including insulator columns extending through third conductive layers. The third region includes a fourth region and a fifth region. In the fourth region, one third conductive layer electrically connects one first conductive layer and one second conductive layer to each other, and in the fifth region, one third conductive layer is connected to a contact plug. A first diameter of a first subset of the insulator columns provided in the fourth region is smaller than a second diameter of a second subset of the insulator columns provided in the fifth region.

公开(公告)号：US11942421B2

公开(公告)日：2024-03-26

申请号：US17880375

申请日：2022-08-03

申请人： Kioxia Corporation

发明人： Kaito Shirai ,  Hanae Ishihara

IPC分类号： H01L23/528 ,  H01L23/522 ,  H10B43/27 ,  H10B43/40 ,  H10B43/35

CPC分类号： H01L23/5226 ,  H01L23/528 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

摘要： A semiconductor memory device includes a semiconductor substrate, a memory cell array, and first and second wirings. The semiconductor substrate includes first region to third region and fourth region to sixth region. The memory cell array includes first conducting layers extending in a second direction from the first region to the third region and laminated in a first direction, first and second semiconductor layers disposed in the first and third regions, extending in the first direction, and opposed to the first conducting layers, first and second contacts disposed in the fourth and sixth regions and extending in the first direction, and a third semiconductor layer disposed in the fifth region and extending in the first direction. The first wiring is connected to the first semiconductor layer and the second contact. The second wiring is connected to the second semiconductor layer and the third contact.

公开(公告)号：US11444022B2

公开(公告)日：2022-09-13

申请号：US17007230

申请日：2020-08-31

申请人： Kioxia Corporation

发明人： Kaito Shirai ,  Hanae Ishihara

IPC分类号： H01L23/528 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11573

摘要： A semiconductor memory device includes a semiconductor substrate, a memory cell array, and first and second wirings. The semiconductor substrate includes first region to third region and fourth region to sixth region. The memory cell array includes first conducting layers extending in a second direction from the first region to the third region and laminated in a first direction, first and second semiconductor layers disposed in the first and third regions, extending in the first direction, and opposed to the first conducting layers, first and second contacts disposed in the fourth and sixth regions and extending in the first direction, and a third semiconductor layer disposed in the fifth region and extending in the first direction. The first wiring is connected to the first semiconductor layer and the second contact. The second wiring is connected to the second semiconductor layer and the third contact.

公开(公告)号：US20210287985A1

公开(公告)日：2021-09-16

申请号：US17007230

申请日：2020-08-31

申请人： Kioxia Corporation

发明人： Kaito Shirai ,  Hanae Ishihara

IPC分类号： H01L23/522 ,  H01L23/528

摘要： A semiconductor memory device includes a semiconductor substrate, a memory cell array, and first and second wirings. The semiconductor substrate includes first region to third region and fourth region to sixth region. The memory cell array includes first conducting layers extending in a second direction from the first region to the third region and laminated in a first direction, first and second semiconductor layers disposed in the first and third regions, extending in the first direction, and opposed to the first conducting layers, first and second contacts disposed in the fourth and sixth regions and extending in the first direction, and a third semiconductor layer disposed in the fifth region and extending in the first direction. The first wiring is connected to the first semiconductor layer and the second contact. The second wiring is connected to the second semiconductor layer and the third contact.

公开(公告)号：US11696446B2

公开(公告)日：2023-07-04

申请号：US17010190

申请日：2020-09-02

申请人： Kioxia Corporation

发明人： Hanae Ishihara

IPC分类号： H10B43/50 ,  H10B43/35 ,  H01L23/535 ,  H01L23/522 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC分类号： H10B43/50 ,  H01L23/5226 ,  H01L23/535 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

摘要： A semiconductor storage device includes a memory cell array including a stacked body having insulating layers and conductive layers that are alternately stacked. The memory cell array includes a cell area and a contact area provided adjacent the cell area. The semiconductor storage device includes: a circuit below the memory cell array; a source layer between the memory cell array and the circuit; a first contact in the contact area, and coupled to the circuit; a second contact over the cell area and the contact area; a first wiring extending in a direction intersecting an extending direction of the second contact in the contact area; a second wiring above the second contact, extending along the second contact in the contact area, and connected to the first wiring; and third contacts between the second wiring and the second contact.

公开(公告)号：US11557605B2

公开(公告)日：2023-01-17

申请号：US17119095

申请日：2020-12-11

申请人： Kioxia Corporation

发明人： Go Oike ,  Hanae Ishihara

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

摘要： According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of first members, and at least one first insulating member. The stacked body is provided on the substrate and includes a plurality of electrode layers. The electrode layers are stacked apart from each other in a first direction and extend in a second direction parallel to an upper surface of the substrate. The first members are provided in the stacked body and extend in the first direction and the second direction. The first insulating member is provided in the stacked body and extends in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate.

公开(公告)号：US11387251B2

公开(公告)日：2022-07-12

申请号：US16800214

申请日：2020-02-25

申请人： Kioxia Corporation

发明人： Shigeki Kobayashi ,  Toru Matsuda ,  Hanae Ishihara

IPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/26

摘要： A memory device includes a substrate, first, second, and third conductive layers, a stack of fourth conductive layers, a memory pillar, and an insulator. The first, second, and third conductive layer are provided above the substrate. The stack of fourth conductive layers is provided above the third conductive layer. The memory pillar extends in the thickness direction through the stack and the third conductive layer and into the second conductive layer in a first region of the memory device. The insulator extends in a thickness direction through the stack, the third conductive layer, and the second conductive layer in a second region of the memory device. The insulator also extends in a second surface direction of the substrate. A thickness of the third conductive layer in a region through which the insulator extends is greater than a thickness of the third conductive layer in the first region.