公开(公告)号：US11868285B2

公开(公告)日：2024-01-09

申请号：US17990169

申请日：2022-11-18

Applicant: Kioxia Corporation

Inventor： Toshio Fujisawa ,  Nobuhiro Kondo ,  Shoji Sawamura ,  Kenichi Maeda ,  Atsushi Kunimatsu

IPC: G06F13/16 ,  G06F13/28 ,  G11C11/00 ,  G11C5/04

CPC classification number: G06F13/1668 ,  G06F13/28 ,  G11C11/005 ,  G11C5/04

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

公开(公告)号：US11537536B2

公开(公告)日：2022-12-27

申请号：US17155415

申请日：2021-01-22

Applicant: Kioxia Corporation

Inventor： Toshio Fujisawa ,  Nobuhiro Kondo ,  Shoji Sawamura ,  Kenichi Maeda ,  Atsushi Kunimatsu

IPC: G06F13/16 ,  G06F13/28 ,  G11C11/00 ,  G11C5/04

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

公开(公告)号：US11868618B2

公开(公告)日：2024-01-09

申请号：US18146237

申请日：2022-12-23

Applicant: KIOXIA CORPORATION

Inventor： Atsushi Kunimatsu ,  Kenichi Maeda

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10 ,  G06F11/14 ,  G06F12/02 ,  G06F13/28 ,  G06F12/1081 ,  G06F12/1027

CPC classification number: G06F3/061 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0638 ,  G06F3/0688 ,  G06F11/1458 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/10 ,  G06F13/28 ,  G06F12/0292 ,  G06F12/1027 ,  G06F12/1081 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.

公开(公告)号：US20230078983A1

公开(公告)日：2023-03-16

申请号：US17990169

申请日：2022-11-18

Applicant: Kioxia Corporation

Inventor： Toshio Fujisawa ,  Nobuhiro Kondo ,  Shoji Sawamura ,  Kenichi Maeda ,  Atsushi Kunimatsu

IPC: G06F13/16 ,  G06F13/28 ,  G11C11/00

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

公开(公告)号：US11537291B2

公开(公告)日：2022-12-27

申请号：US17200111

申请日：2021-03-12

Applicant: Kioxia Corporation

Inventor： Atsushi Kunimatsu ,  Kenichi Maeda

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10 ,  G06F11/14 ,  G06F12/02 ,  G06F13/28 ,  G06F12/1081 ,  G06F12/1027

Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.