公开(公告)号：US20240099013A1

公开(公告)日：2024-03-21

申请号：US18519872

申请日：2023-11-27

Applicant: Kioxia Corporation

Inventor： Yoshiaki FUKUZUMI ,  Hideaki AOCHI ,  Mie MATSUO ,  Kenichiro YOSHII ,  Koichiro SHINDO ,  Kazushige KAWASAKI ,  Tomoya SANUKI

IPC: H10B43/40 ,  H01L21/18 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50

CPC classification number: H10B43/40 ,  H01L21/185 ,  H01L21/76898 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50 ,  H01L2224/08145

Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.