中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

31 records (took 0.016 seconds)

    MEMORY SYSTEM
    2.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240086077A1

    公开(公告)日：2024-03-14

    申请号：US18181824

    申请日：2023-03-10

    Applicant: Kioxia Corporation

    Inventor： Tomoya SANUKI ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.

    DATA LATCH CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE
    3.
    发明公开
    DATA LATCH CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE 审中-公开

    公开(公告)号：US20230197160A1

    公开(公告)日：2023-06-22

    申请号：US17898868

    申请日：2022-08-30

    Applicant: KIOXIA CORPORATION

    Inventor： Tomoya SANUKI ,  Koji KOHARA ,  Keisuke NAKATSUKA

    IPC: G11C16/10

    CPC classification number: G11C16/10

    Abstract: A data latch circuit includes a first transistor of a first conductivity type and a second transistor of the first conductivity type, and a third transistor of a second conductivity type and a fourth transistor of the second conductivity type. The third and fourth transistors are controlled to perform a first control operation to store data in the data latch circuit and to perform a second control operation to read the stored data.

    MEMORY DEVICE CONFIGURED TO PERFORM A SEARCH OPERATION
    5.
    发明公开
    MEMORY DEVICE CONFIGURED TO PERFORM A SEARCH OPERATION 审中-公开

    公开(公告)号：US20240304239A1

    公开(公告)日：2024-09-12

    申请号：US18587935

    申请日：2024-02-26

    Applicant: Kioxia Corporation

    Inventor： Tomoya SANUKI ,  Yasuhito YOSHIMIZU

    IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/408

    CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4085

    Abstract: A memory device includes a bit line, a source line, a first string in which a plurality of first memory cells are connected in series between the bit line and the source line, and a control circuit. The control circuit performs a sense operation for a search operation to determine if search data is stored in the plurality of first memory cells by supplying voltages to a plurality of word lines respectively corresponding to the plurality of first memory cells based on the search data and determining a similarity between the search data and data actually stored in the plurality of first memory cells based on a change in voltage of the bit line caused by current flowing between the bit line and the source line via the first string.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230080259A1

    公开(公告)日：2023-03-16

    申请号：US18056508

    申请日：2022-11-17

    Applicant: Kioxia Corporation

    Inventor： Tomoya SANUKI ,  Hiroshi MAEJIMA ,  Tetsuaki UTSUMI

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210296298A1

    公开(公告)日：2021-09-23

    申请号：US17005535

    申请日：2020-08-28

    Applicant: KIOXIA CORPORATION

    Inventor： Tomoya SANUKI ,  Keisuke NAKATSUKA ,  Hiroshi MAEJIMA ,  Kenichiro YOSHII ,  Takashi MAEDA ,  Hideo WADA

    IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

    Abstract: A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.

Patent Agency Ranking