公开(公告)号：US20220293138A1

公开(公告)日：2022-09-15

申请号：US17470955

申请日：2021-09-09

Applicant: Kioxia Corporation

Inventor： Kazushige KAWASAKI ,  Masayuki MIURA ,  Hideko MUKAIDA

IPC: G11C5/06 ,  H01L23/10

Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0≤t1

公开(公告)号：US20240099013A1

公开(公告)日：2024-03-21

申请号：US18519872

申请日：2023-11-27

Applicant: Kioxia Corporation

Inventor： Yoshiaki FUKUZUMI ,  Hideaki AOCHI ,  Mie MATSUO ,  Kenichiro YOSHII ,  Koichiro SHINDO ,  Kazushige KAWASAKI ,  Tomoya SANUKI

IPC: H10B43/40 ,  H01L21/18 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50

CPC classification number: H10B43/40 ,  H01L21/185 ,  H01L21/76898 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50 ,  H01L2224/08145

Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

公开(公告)号：US20230207520A1

公开(公告)日：2023-06-29

申请号：US17934135

申请日：2022-09-21

Applicant: Kioxia Corporation

Inventor： Masayuki MIURA ,  Kazuma HASEGAWA ,  Kazushige KAWASAKI

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L24/48 ,  H01L24/32 ,  H01L24/73 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48149 ,  H01L2224/48225 ,  H01L2924/182 ,  H01L21/563

Abstract: A semiconductor device includes a wiring substrate inside which a wiring layer is provided, a plurality of first semiconductor chips stacked in a shifted manner on the wiring substrate and each provided with a connection terminal on a surface facing the wiring substrate, and a second semiconductor chip having a function different from functions of the first semiconductor chips and provided on the wiring substrate on a side where the connection terminals are electrically connected to the wiring substrate.