公开(公告)号：US20240099013A1

公开(公告)日：2024-03-21

申请号：US18519872

申请日：2023-11-27

Applicant: Kioxia Corporation

Inventor： Yoshiaki FUKUZUMI ,  Hideaki AOCHI ,  Mie MATSUO ,  Kenichiro YOSHII ,  Koichiro SHINDO ,  Kazushige KAWASAKI ,  Tomoya SANUKI

IPC: H10B43/40 ,  H01L21/18 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50

CPC classification number: H10B43/40 ,  H01L21/185 ,  H01L21/76898 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50 ,  H01L2224/08145

Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

公开(公告)号：US20230267075A1

公开(公告)日：2023-08-24

申请号：US18310597

申请日：2023-05-02

Applicant: KIOXIA CORPORATION

Inventor： Kazuhiro FUKUTOMI ,  Kenichiro YOSHII ,  Shinichi KANNO ,  Shigehiro ASANO

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/00 ,  G06F12/16

CPC classification number: G06F12/0246 ,  G06F3/064 ,  G06F12/00 ,  G06F12/16 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0611 ,  G06F3/0688 ,  G06F2212/7205 ,  G06F3/0608 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/0638 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/7202

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

公开(公告)号：US20220156182A1

公开(公告)日：2022-05-19

申请号：US17590310

申请日：2022-02-01

Applicant: KIOXIA CORPORATION

Inventor： Kazuhiro FUKUTOMI ,  Kenichiro YOSHII ,  Shinichi KANNO ,  Shigehiro ASANO

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/00 ,  G06F12/16

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

公开(公告)号：US20240256442A1

公开(公告)日：2024-08-01

申请号：US18624930

申请日：2024-04-02

Applicant: KIOXIA CORPORATION

Inventor： Kazuhiro FUKUTOMI ,  Kenichiro YOSHII ,  Shinichi KANNO ,  Shigehiro ASANO

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/00 ,  G06F12/16

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/16 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0638 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/0688 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/7202 ,  G06F2212/7205

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

公开(公告)号：US20230281078A1

公开(公告)日：2023-09-07

申请号：US18316531

申请日：2023-05-12

Applicant: KIOXIA CORPORATION

Inventor： Kenichiro YOSHII ,  Shinichi KANNO

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/1009

CPC classification number: G06F11/1068 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/1009 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0604 ,  G06F3/0656 ,  G06F2212/1044

Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.

公开(公告)号：US20210296298A1

公开(公告)日：2021-09-23

申请号：US17005535

申请日：2020-08-28

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Keisuke NAKATSUKA ,  Hiroshi MAEJIMA ,  Kenichiro YOSHII ,  Takashi MAEDA ,  Hideo WADA

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.