公开(公告)号：US20240057338A1

公开(公告)日：2024-02-15

申请号：US18176525

申请日：2023-03-01

Applicant: Kioxia Corporation

Inventor： Wataru HASEGAWA ,  Takuya KONNO ,  Sachiyo ITO ,  Ken FURUBAYASHI

IPC: H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H01L23/5226 ,  H01L23/5283

Abstract: According to one embodiment, a memory device includes: a first layer stack including first insulating layers arranged in a first direction and spaced apart from one another; second and third layer stacks, each including conductive layers spaced apart from one another and provided at levels of layers identical to the first insulating layers, respectively, and being spaced apart from each other; a memory pillar extending in the first direction in the third layer stack, a portion of the memory pillar intersecting each of the conductive layers functioning as a memory cell; a first member in contact with the first and second layer stacks between the first and second layer stacks and extending in a second direction; and a second member in contact with the second and third layer stacks between the second and third layer stacks and extending in the second direction.