公开(公告)号：US20220336531A1

公开(公告)日：2022-10-20

申请号：US17857482

申请日：2022-07-05

Applicant: Kioxia Corporation

Inventor： Takuya KONNO

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.

公开(公告)号：US20240057338A1

公开(公告)日：2024-02-15

申请号：US18176525

申请日：2023-03-01

Applicant: Kioxia Corporation

Inventor： Wataru HASEGAWA ,  Takuya KONNO ,  Sachiyo ITO ,  Ken FURUBAYASHI

IPC: H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H01L23/5226 ,  H01L23/5283

Abstract: According to one embodiment, a memory device includes: a first layer stack including first insulating layers arranged in a first direction and spaced apart from one another; second and third layer stacks, each including conductive layers spaced apart from one another and provided at levels of layers identical to the first insulating layers, respectively, and being spaced apart from each other; a memory pillar extending in the first direction in the third layer stack, a portion of the memory pillar intersecting each of the conductive layers functioning as a memory cell; a first member in contact with the first and second layer stacks between the first and second layer stacks and extending in a second direction; and a second member in contact with the second and third layer stacks between the second and third layer stacks and extending in the second direction.

公开(公告)号：US20240008273A1

公开(公告)日：2024-01-04

申请号：US18151921

申请日：2023-01-09

Applicant: Kioxia Corporation

Inventor： Rikyu IKARIYAMA ,  Shinya OKUDA ,  Takuya KONNO

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: According to one embodiment, a semiconductor device manufacturing method includes forming a stacked film with alternating first-type sacrificial layers and second-type sacrificial layers, then removing the first-type sacrificial layers from the stacked film to leave the second-type sacrificial layers with spaces therebetween. The second-type sacrificial layers are then each replaced with an insulating layer after removing the first-type sacrificial layers. After the second-type sacrificial layers are replaced with the insulating layer, a conductive layer is formed inside the spaces formed by removing the first-type sacrificial layers.

公开(公告)号：US20230317632A1

公开(公告)日：2023-10-05

申请号：US17883690

申请日：2022-08-09

Applicant: Kioxia Corporation

Inventor： Mayuka OJIMA ,  Sachiyo ITO ,  Takuya KONNO

IPC: H01L23/00 ,  H01L23/58 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device according to an embodiment includes a substrate, a transistor, an insulating layer, and a first sealing portion. The substrate includes a first region, and a second region provided to surround an outer periphery of the first region. The transistor is provided on the substrate in the first region. The insulating layer is provided above the transistor and over the first region and the second region. The first sealing portion is provided to divide the insulating layer and surround the outer periphery of the first region in the second region. The first sealing portion includes a first void.

公开(公告)号：US20240324213A1

公开(公告)日：2024-09-26

申请号：US18595315

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Takuya KONNO

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A semiconductor memory device includes a stacked body including a plurality of conductive layers stacked in a first direction, a pillar structure array including a plurality of pillar structures each extending in the first direction in the stacked body and arranged in a second direction and a third direction, the plurality of pillar structures including a plurality of first pillar structures, each of which is a part of a string of memory cell transistors, a first plate-shaped structure extending in the first and second directions in the stacked body, a second plate-shaped structure extending in the first and third directions in the stacked body and disposed along an end portion of the pillar structure array in the second direction, and a support structure extending in the first direction in the stacked body and disposed where the first plate-shaped structure and the second plate-shaped structure intersect.

公开(公告)号：US20230062835A1

公开(公告)日：2023-03-02

申请号：US17679896

申请日：2022-02-24

Applicant: KIOXIA CORPORATION

Inventor： Takuya KONNO ,  Sachiyo ITO

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: According to one embodiment, a semiconductor device includes a first substrate, a second substrate joined to the first substrate. A first region of the semiconductor device that includes a peripheral circuit is between the first substrate and the second substrate. A second region that includes a memory cell array is between the first region and the second substrate. A layer that is embedded in the second substrate has a Young's modulus that is higher than that of silicon and/or an internal stress that is higher than that of silicon oxide.

公开(公告)号：US20220384363A1

公开(公告)日：2022-12-01

申请号：US17680126

申请日：2022-02-24

Applicant: KIOXIA CORPORATION

Inventor： Ken FURUBAYASHI ,  Sachiyo ITO ,  Takuya KONNO

IPC: H01L23/00 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor storage device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked along a stacking direction, and a plurality of first pillars extending in the stacked body along the stacking direction to form memory cells at intersections with at least some of the plurality of conductive layers. The stacked body includes a stair portion in which the plurality of conductive layers are stacked in a stepped manner at a position separated from the plurality of first pillars in a first direction intersecting the stacking direction. At least a lowermost insulating layer of the plurality of insulating layers has at least one bending portion bent in the stacking direction at an end of the plurality of conductive layers in the stair portion along the first direction.