公开(公告)号：US20230083158A1

公开(公告)日：2023-03-16

申请号：US17682889

申请日：2022-02-28

Applicant: Kioxia Corporation

Inventor： Kenichi MATOBA ,  Takahiro TSURUDO ,  Yoshiaki TAKAHASHI ,  Yoichi MIZUTA ,  Yoshifumi SHIMAMURA ,  Toru OZAWA ,  Takumi KOSAKI ,  Kouji NAKAO

IPC: H01L27/11529 ,  H01L27/108

Abstract: A semiconductor device includes an active region, and an edge seal formed on at least a portion of an outer edge of the active region. The edge seal includes a first stacked body having a first conductive layer, and a second stacked body having a second conductive layer. The first conductive layer is coupled to a first voltage, the second conductive layer is coupled to a second voltage different from the first voltage, and the first conductive layer faces the second conductive layer.

公开(公告)号：US20250149464A1

公开(公告)日：2025-05-08

申请号：US19012434

申请日：2025-01-07

Applicant: Kioxia Corporation

Inventor： Yoichi MIZUTA ,  Takahiro TSURUDO ,  Yoshiaki TAKAHASHI ,  Kenichi MATOBA ,  Yoshifumi SHIMAMURA ,  Toru OZAWA ,  Takumi KOSAKI ,  Kouji NAKAO

IPC: H01L23/544 ,  H01L21/66 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: According to one embodiment, a semiconductor device includes a circuit pattern including a plurality of unit patterns that are disposed in a repeating manner in at least one direction. The semiconductor device includes a discrimination pattern provided in the circuit pattern and configured to discriminate the unit patterns from each other.

公开(公告)号：US20230307395A1

公开(公告)日：2023-09-28

申请号：US17813812

申请日：2022-07-20

Applicant: Kioxia Corporation

Inventor： Nobuaki OKADA ,  Masaki UNNO ,  Hiroyuki TAKENAKA ,  Yoshiaki TAKAHASHI ,  Hiroshi MAEJIMA

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device comprises a first chip and a second chip bonded via bonding electrodes. The first chip comprises a semiconductor substrate. The second chip comprises: first conductive layers; semiconductor layers facing the first conductive layers; a first wiring layer including bit lines; a second wiring layer including wirings; and a third wiring layer including first bonding electrodes. The wirings each comprise: a first portion provided in a region overlapping one of the bit lines, and is electrically connected to the one of the bit lines; and a second portion provided in a region overlapping one of the first bonding electrodes, and is connected to the one of the first bonding electrodes. At least some of these wirings comprise a third portion connected to one end portion in a second direction of the first portion and one end portion in the second direction of the second portion.

公开(公告)号：US20220285284A1

公开(公告)日：2022-09-08

申请号：US17412022

申请日：2021-08-25

Applicant: Kioxia Corporation

Inventor： Yoichi MIZUTA ,  Takahiro TSURUDO ,  Yoshiaki TAKAHASHI ,  Kenichi MATOBA ,  Yoshifumi SHIMAMURA ,  Toru OZAWA ,  Takumi KOSAKI ,  Kouji NAKAO

IPC: H01L23/544 ,  H01L21/768 ,  H01L21/66

Abstract: According to one embodiment, a semiconductor device includes a circuit pattern including a plurality of unit patterns that are disposed in a repeating manner in at least one direction. The semiconductor device includes a discrimination pattern provided in the circuit pattern and configured to discriminate the unit patterns from each other.

公开(公告)号：US20220093186A1

公开(公告)日：2022-03-24

申请号：US17336772

申请日：2021-06-02

Applicant: Kioxia Corporation

Inventor： Toru OZAWA ,  Kouji NAKAO ,  Yoichi MIZUTA ,  Kiyofumi SAKURAI ,  Youichi MAGOME ,  Yoshiaki TAKAHASHI

IPC: G11C16/30

Abstract: A semiconductor storage device of an embodiment includes a wiring layer M1 and a wiring layer M2. The wiring layer M1 includes a signal line through which a data signal is transferred, and a plurality of dummy patterns formed of a material same as a material of the signal line. The wiring layer M2 includes a voltage supply line through which voltage Vdd is supplied and another voltage supply line through which voltage Vss is supplied. Each of the dummy patterns is electrically connected with any one of the voltage supply lines. In a dummy pattern disposed adjacent to the signal line, a surface facing the signal line is constituted by a first surface positioned at a first distance to the signal line and a second surface positioned at a second distance to the signal line, the second distance being different from the first distance.